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Software Hardware Co-Optimized BFS on FPGAs

Authors:
Zachary Sherer

University of Massachusetts Lowell, Lowell, MA, USA

University of Massachusetts Lowell, Lowell, MA, USA
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,
Eric Finnerty

University of Massachusetts Lowell, Lowell, MA, USA

University of Massachusetts Lowell, Lowell, MA, USA
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,
Yan Luo

University of Massachusetts Lowell, Lowell, MA, USA

University of Massachusetts Lowell, Lowell, MA, USA
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,
Hang Liu

University of Massachusetts Lowell, Lowell, MA, USA

University of Massachusetts Lowell, Lowell, MA, USA
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Authors Info & Claims

FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysFebruary 2019Pages 190https://doi.org/10.1145/3289602.3293982

Published:20 February 2019Publication History

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FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 190

ABSTRACT

No abstract available.

Index Terms

Software Hardware Co-Optimized BFS on FPGAs
1. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Graph algorithms

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Published in
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
February 2019
360 pages
ISBN:9781450361378
DOI:10.1145/3289602
General Chair:
Kia Bazargan
Univ. of Minnesota, USA
,
Program Chair:
Stephen Neuendorffer
Xilinx, USA
Copyright © 2019 Owner/Author
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.
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Association for Computing Machinery
New York, NY, United States
Publication History
- Published: 20 February 2019
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Author Tags
bfs
fpga
graph computing
graph partition
hardware-software codesign
soc
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