ABSTRACT
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown that they can also be used to implement logic very efficiently. This previous work has only considered single-port arrays. Many current FPGAs, however, contain dual-port arrays. In this paper we present an algorithm that maps logic to these dual-port arrays. Our algorithm can either optimize area with no regard for circuit speed, or optimize area under the constraint that the combinational depth of the circuit does not increase. Experimental results show that, on average, our algorithm packs between 29% and 35% more logic than an algorithm that targets single-port arrays. We also show, however, that even with this algorithm, dual-port arrays are still not as area-efficient as single-port arrays when implementing logic.
- 1.Altera Corporation, FLEX IOK Embedded Programmable Logic Family Data Sheet, ver. 4.01, June 1999.Google Scholar
- 2.Altera Corporation, FLEX IOKE Embedded Programmable Logic Family Data Sheet, vet. 2.01, June 1999.Google Scholar
- 3.Altera Corporation, APEX 20K Programmable Logic Device Family Data Sheet, ver. 2.0, May 1999.Google Scholar
- 4.Xilinx, Inc., Virtex 2.5 V Field Programmable Gate Arrays, vet 1.6, July 1999.Google Scholar
- 5.Lattice Semiconductor, Vantis VF1 FPGA Data Sheet, November 1998.Google Scholar
- 6.Actel Corporation, Data sheet: ProASIC 500K Family, June 1999.Google Scholar
- 7.Actel Corporation, MX FPGA Data Sheet, January 1999.Google Scholar
- 8.Actel Corporation, Datasheet: Integrator Series FPGAs: 1200XL and 3200DX Families, January 1998.Google Scholar
- 9.S. J. E. Wilton, "SMAP: heterogeneous technology mapping for FPGAs with embedded memory arrays," in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 171-178, February 1998. Google ScholarDigital Library
- 10.J. Cong and S. Xu, "Technology mapping for FPGAs with embedded memory blocks;' in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 179-187,February 1998. Google ScholarDigital Library
- 11.J. Cong and Y. Ding, "Combinational logic synthesis for LUT based field programmable gate arrays," ACM Transactions on Design Automation of Electronic Systems, vol. 1, pp. 145-204, April 1996. Google ScholarDigital Library
- 12.R. Hitchcock, G. Smith, and D. Cheng, "Timing analysis of computer hardware;' IBM Journal of Research and Development, pp. 100-105, January 1983.Google Scholar
- 13.E. Sentovich, "SIS: A system for sequential circuit analysis;' Tech. Rep. UCB/ERL M92/41, Electronics Research Laboratory, University of Califomia, Berkeley, May 1992.Google Scholar
- 14.J. Cong and Y. Ding, "FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs;' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1-12, January 1994.Google ScholarDigital Library
- 15.S. J. E. Wilton, "Heterogeneous technology mapping for area reduction in fpgas with embedded memory arrays;' to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000.Google ScholarDigital Library
Index Terms
- Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays
Recommendations
Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
It has become clear that large embedded configurable memory arrays will be essential in future field programmable gate arrays (FPGAs). Embedded arrays provide high-density high-speed implementations of the storage parts of circuits, Unfortunately, they ...
N-port memory mapping for LUT-based FPGAs
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysAs current FPGAs grow in logic capacity, they are widely used to implement entire systems. In some specific applications, such as our embedded multi-core processor TriBA[1],user memory models are not limited to single-port or dual-port. Thus, we need a ...
Mapping N-Port Memory with Dual-Port Array
CSIE '09: Proceedings of the 2009 WRI World Congress on Computer Science and Information Engineering - Volume 03It has become clear that on-chip storage is criticalfor most applications on FPGAs. In order to utilize onchip storage efficiently, scholars have done some researches on implementing user memory models with embedded single-port and dual-port arrays. ...
Comments