Masahiro Fujita
ABSTRACT
We first present historical view on the techniques for two-level and multi-level logic optimizations, and discuss the practical issues with respect to them. Then the techniques for sequential optimizations are briefly reviewed. Based on them, a new approach which formulates ECO (Engineering Change Order) as partial logic synthesis is discussed. Finally a new formulation of an automatic generation of parallel/distributed computing from sequential one is introduced with an application example.
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- Masahiro Fujita and Alan Mishchenko. 2014. Efficient SAT-based ATPG techniques for all multiple stuck-at faults. In Proceedings of International Test Conference. 1--10.Google ScholarCross Ref
- Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, and Alan Mishchenko. 2015. Incremental ATPG methods for multiple faults under multiple fault models. In Proceedings of International Symposium on Quality Electronic Design . Santa Clara, USA, 177--180.Google ScholarCross Ref
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- Yukio Miyasaka, Ashish Mittal, and Masahiro Fujita. 2019. Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. In Proceedings of International Symposium on Quality Electronic Design. Santa Clara, USA.Google ScholarCross Ref
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- Peikun Wang, Amir Masoud Gharehbaghi, and Masahiro Fujita. 2019. An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults. In Proceedings of IEEE VLSI Test Symposium. Monterey, USA.Google Scholar
Index Terms
- Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions
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