skip to main content
10.1145/330855.331038acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article
Free Access

Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching

Authors Info & Claims
Published:02 March 2000Publication History

ABSTRACT

In non-Manhattan geometry layout extraction, polygon to trapezoid decomposition is an indispensable step. Its efficiency and the organization of generated trapezoids significantly affect the performance of layout extractors. We present a new polygon to trapezoid decomposition algorithm used in our layout extractor iLEX. The concept of edge pair and scanline interval are introduced to provide improved efficiency over conventional scanline algorithms. Definitions for trapezoid corner stitches are provided as well as integrated algorithms on corner stitching trapezoids generated. Complexity analysis shows that our scanline algorithm has an expected computation time of Ο(n log n), and an expected space of Ο(√n), where n is the number of non-vertical edges in the given layout.

References

  1. 1.J. L. Bentley and T. A. Ottmann. Algorithms for reporting and counting geometric intersections. IEEE Transactions on Computing, 6-28(9):643-647, September 1979.Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.K. W. Chiang, S. Nahar, and C. Y. Lo. Time-efficient vlsi artwork analysis algorithms in goalie2. IEEE Transactions on Computer-Aided Design, 8(6):640-648, June 1989.Google ScholarGoogle ScholarCross RefCross Ref
  3. 3.U. Lauther. An o(nlogn) algorithm for boolean mask operations. In 18th Design Automation Conference, pages 555-562, 1981. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4.D. Marple, M. Smulders, and H. Hegen. Tailor: A layout system based on trapezoidal corner stitching. IEEE Transaction on Computer-Aided Design, 9(1):66- 90, January 1990.Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5.J. K. Ousterhout. Corner stitching: A data-structuring technique for vlsi layout tools. IEEE Transactions on Computer-Aided Design, CAD-3(1):87-100, January 1984.Google ScholarGoogle Scholar
  6. 6.W. S. Scott and J. K. Ousterhout. Magic's circuit extractor. In 22nd Design Automation Conference, pages 286-292, 1985. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7.N. P. van der Meijs and A. J. van Genderen. An efficient algorithm for analysis of non-orthogonal layout. In IEEE International Symposium on Circuits and Systems, pages 47-52, 1989.Google ScholarGoogle ScholarCross RefCross Ref

Index Terms

  1. Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in
        • Published in

          cover image ACM Conferences
          GLSVLSI '00: Proceedings of the 10th Great Lakes symposium on VLSI
          March 2000
          196 pages
          ISBN:1581132514
          DOI:10.1145/330855

          Copyright © 2000 ACM

          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 2 March 2000

          Permissions

          Request permissions about this article.

          Request Permissions

          Check for updates

          Qualifiers

          • Article

          Acceptance Rates

          Overall Acceptance Rate312of1,156submissions,27%

          Upcoming Conference

          GLSVLSI '24
          Great Lakes Symposium on VLSI 2024
          June 12 - 14, 2024
          Clearwater , FL , USA

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader