ABSTRACT
The Tunable Delay Line (TDL) is the most important building block in a modern cell-based timing circuit such as Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL). In previously proposed TDLs, one dilemma exists -- they cannot be both power efficient and environmentally adaptive at the same time. In this paper, we present an effective solution for such a dilemma - a novel "ping-pong delay line" architecture. The idea is to use two small cell-based delay lines operated in a synergistic manner in the sense that they exchange the "role of command" dynamically like in a ping-pong game, and thereby jointly reacting to severe environmental changes over a very wide range. This proposed ping-pong delay line has been incorporated in a Delay-Locked Loop (DLL) design, to demonstrate its advantages by post-layout simulation.
- T. Olsson and P. Nilsson, "A Digitally Controlled PLL for SoC Applications," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751--760, May, 2004.Google ScholarCross Ref
- D. Sheng, C.-C Chung and C.-Y. Lee, "An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications," IEEE Trans. on Circuits Syst., Exp. Briefs, vol. 54, no. 11, Nov. 2007.Google Scholar
- P.-C. Huang and S.-Y. Huang, "Cell-Based Delay Locked Loop Compiler," Proc. of Int'l SoC Design Conf., pp. 91--92, Oct. 2016.Google Scholar
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