Abhishek Vashist
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Abstract
On-chip wireless interconnects have been demonstrated to improve the performance and energy consumption of data communication in Network-on-Chips (NoCs). However, the wireless interfaces (WIs) can be defective, rendering these broken links severely affect the performance. This makes manufacturing test of the WIs critical. While analog testing of the transceivers is possible, such methodologies are impractical in a Wireless NoC (WiNoC) due to large overheads. In addition to testing, security is another prominent challenge in WiNoCs, as the security breach can happen due to embedded hardware Trojans or through external attacker exploiting the wireless medium. The typical security measures used in general wireless networks are not practical in a WiNoC due to unique network architectures and performance requirements of such a system. However, both testing and security defense can potentially leverage a basic monitoring framework which, can detect malfunctions or anomalies. Based on this idea, we propose a unified architecture for testing and attack detection and protection of on-chip wireless interconnects. We adopt a Built-In-Self Test (BIST) methodology to enable online monitoring of the wireless interconnects which can also be reused for monitoring the security threats. We focus on manufacturing defects of the WIs for testing and persistent jamming attack for the security measures, as this kind of attack is most likely on wireless communication systems. The BIST methodology is capable of detecting faults in the wireless links with a low aliasing probability of 2.32× 10−10. Additionally, the proposed unified architecture is able to detect the persistent jamming with an accuracy of 99.87% and suffer < 3% communication bandwidth degradation even in the presence of attacks from either internal or external sources.
- V. Akilandeswari and S. M. Shalinie. 2012. Probabilistic neural network based attack traffic classification. In Int. Conf. on Advanced Computing.Google Scholar
- Luca Benini and Giovanni De Micheli. 2002. Networks on chips: A new SoC paradigm. Computer 35, 1 (Jan 2002), 70--78.Google ScholarDigital Library
- M. Bühler, J. Koehl, J. Bickford, J. Hibbeler, U. Schlichtmann, R. Sommer, M. Pronath, and A. Ripp. 2006. DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. In Design, Automation and Test in Europe.Google Scholar
- Kevin Chang, Sujay Deb, Amlan Ganguly, Xinmin Yu, Suman Prasad Sah, Partha Pratim Pande, Benjamin Belzer, and Deukhyoun Heo. 2012. Performance evaluation and design trade-offs for wireless network-on-chip architectures. J. Emerg. Technol. Comput. Syst. 8, 3 (Aug 2012), 23:1--23:25.Google ScholarDigital Library
- Kyungwook Chang, Sai Pentapati, Da Eun Shim, and Sung Kyu Lim. 2018. Road to high-performance 3D ICs: Performance optimization methodologies for monolithic 3D ICs. In International Symposium on Low Power Electronics and Design.Google ScholarDigital Library
- Sai Vineel Reddy Chittamuru, Dharanidhar Dang, Sudeep Pasricha, and Rabi N. Mahapatra. 2018. BiGNoC: Accelerating big data computing with application-specific photonic network-on-chip architectures. IEEE Trans. Parallel Distrib. Syst. 29, 11 (2018), 2402--2415.Google ScholarDigital Library
- S. V. R. Chittamuru, I. G. Thakkar, and S. Pasricha. 2018. HYDRA: Heterodyne crosstalk mitigation with double microring resonators and data encoding for photonic NoCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, 1 (Jan 2018), 168--181.Google ScholarCross Ref
- Sai Mano P. D., J. Lin, S. Zhu, Y. Yin, X. Liu, X. Huang, C. Song, W. Zhang, M. Yan, Z. Yu, and H. Yu. 2017. A scalable network-on-chip microprocessor with 2.5D integrated memory and accelerator. IEEE Transactions on Circuits and Systems I: Regular Papers 64, 6 (June 2017), 1432--1443.Google Scholar
- Sai Manoj P. D., H. Yu, Y. Shang, C. S. Tan, and S. K. Lim. 2013. Reliable 3-D clock-tree synthesis considering nonlinear capacitive TSV model with electrical-thermal-mechanical coupling. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 32, 11 (Nov 2013), 1734--1747.Google Scholar
- Sujay Deb, Kevin Chang, Xinmin Yu, Suman Prasad Sah, Miralem Cosic, Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, and Deukhyoun Heo. 2013. Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects. IEEE Trans. Comput. 62, 12 (Dec 2013), 2382--2396.Google ScholarDigital Library
- S. Deb, A. Ganguly, P. P. Pande, B. Belzer, and D. Heo. 2012. Wireless NoC as interconnection backbone for multicore chips: Promises and challenges. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2, 2 (June 2012), 228--239.Google ScholarCross Ref
- D. DiTomaso, A. Kodi, D. Matolak, S. Kaya, S. Laha, and W. Rayess. 2013. Energy-efficient adaptive wireless NoCs architecture. In IEEE/ACM Int. Symp. on Networks-on-Chip.Google Scholar
- Rohan Doshi, Noah Apthorpe, and Nick Feamster. 2018. Machine learning DDoS detection for consumer Internet of Things devices. CoRR abs/1804.04159 (2018).Google Scholar
- Jose Duato, Sudhakar Yalamanchili, and Ni Lionel. 2002. Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers Inc.Google ScholarDigital Library
- K. Duraisamy and P. P. Pande. 2017. Enabling high-performance SMART NoC architectures using on-chip wireless links. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, 12 (Dec 2017), 3495--3508.Google Scholar
- E. S. Erdogan and S. Ozev. 2010. Detailed characterization of transceiver parameters through loop-back-based BiST. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, 6 (2010), 901--911.Google ScholarDigital Library
- S. Evain and J. Diguet. 2005. From NoC security analysis to design solutions. In IEEE Workshop on Signal Processing Systems Design and Implementation.Google Scholar
- B. Fu and P. Ampadu. 2009. Burst error detection hybrid ARQ with crosstalk-delay reduction for reliable on-chip interconnects. In IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems.Google Scholar
- Amlan Ganguly, Mohsin Yusuf Ahmed, and Anuroop Vidapalapati. 2012. A denial-of-service resilient wireless NoC architecture. In Great Lakes Symp. on VLSI.Google ScholarDigital Library
- C. Grecu, A. Ivanov, R. Saleh, and P. P. Pande. 2007. Testing network-on-chip communication fabrics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, 12 (Dec 2007), 2201--2214.Google ScholarDigital Library
- C. Grecu, P. Pande, A. Ivanov, and R. Saleh. 2006. BIST for network-on-chip interconnect infrastructures. In IEEE VLSI Test Symposium.Google Scholar
- Mohammad Hosseinabady, Atefe Dalirsani, and Zainalabedin Navabi. 2007. Using the inter- and intra-switch regularity in NoC switch testing. In Design, Automation and Test in Europe.Google Scholar
- R. JayashankaraShridevi, C. Rajamanikkam, K. Chakraborty, and S. Roy. 2016. Catching the Flu: Emerging threats from a third party power management unit. In ACM/EDAC/IEEE Design Automation Conf.Google Scholar
- E. Kakoulli, V. Soteriou, and T. Theocharides. 2012. Intelligent hotspot prediction for network-on-chip-based multicore systems. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 31, 3 (March 2012), 418--431.Google ScholarDigital Library
- M. Kar and T. Krishna. 2017. A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance. In IEEE/ACM International Conference on Computer-Aided Design.Google Scholar
- Reyhaneh Karimazad and Ahmad Faraahi. 2011. An anomaly-based method for DDoS attacks detection using RBF neural networks. In Int. Conf. on Network and Electronics Engineering.Google Scholar
- B. Lebiednik, S. Abadal, H. Kwon, and T. Krishna. 2018. Architecting a secure wireless network-on-chip. In IEEE/ACM International Symposium on Networks-on-Chip (NOCS).Google Scholar
- Y. Lee and S. K. Lim. 2011. Co-optimization and analysis of signal, power, and thermal interconnects in 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, 11 (Nov 2011), 1635--1648.Google Scholar
- X. Li, K. Duraisamy, J. Baylon, T. Majumder, G. Wei, P. Bogdan, D. Heo, and P. P. Pande. 2017. A reconfigurable wireless NoC for large scale microbiome community analysis. IEEE Trans. Comput. 66, 10 (Oct 2017), 1653--1666.Google ScholarDigital Library
- J. Lin, H. Wu, Y. Su, L. Gao, A. Sugavanam, J. E. Brewer, and K. K. O. 2007. Communication using antennas fabricated in silicon integrated circuits. IEEE J. of Solid-State Circuits 42, 8 (Aug 2007), 1678--1687.Google Scholar
- J. Lin, S. Zhu, Z. Yu, D. Xu, Sai Manoj P. D., and H. Yu. 2015. A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer. In IEEE Custom Integrated Circuits Conf.Google Scholar
- Partha Pratim Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh. 2005. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. on Computers 54, 8 (Aug 2005), 1025--1040.Google ScholarDigital Library
- A. Pathania and J. Henkel. 2018. Task scheduling for many-cores with S-NUCA caches. In Design, Automation Test in Europe Conference.Google Scholar
- Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, and Jörg Henkel. 2017. Defragmentation of tasks in many-core architecture. ACM Trans. Archit. Code Optim. 14, 1 (Mar 2017), 2:1--2:21.Google ScholarDigital Library
- Fernando Pereñíguez García and José L. Abellán. 2017. Secure communications in wireless network-on-chips. In Int. W. on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems.Google Scholar
- P. Arun Raj Kumar and S. Selvakumar. 2011. Distributed denial of service attack detection using an ensemble of neural classifier. Comput. Commun. 34, 11 (July 2011), 1328--1341.Google ScholarCross Ref
- Martin Rapp, Anuj Pathania, and Jörg Henkel. 2018. Pareto-optimal power- and cache-aware task mapping for many-cores with distributed shared last-level cache. In International Symposium on Low Power Electronics and Design.Google ScholarDigital Library
- M. Richter and K. Chakrabarty. 2012. Test pin count reduction for NoC-based test delivery in multicore SOCs. In Design, Automation Test in Europe Conference Exhibition (DATE).Google Scholar
- M. S. Shamim, N. Mansoor, R. S. Narde, V. Kothandapani, A. Ganguly, and J. Venkataraman. 2017. A wireless interconnection framework for seamless inter and intra-chip communication in multichip systems. IEEE Trans. Comput. 66, 3 (Mar 2017), 389--402.Google ScholarDigital Library
- C. Stroud, J. Morton, T. Islam, and H. Alassaly. 2003. A mixed-signal built-in self-test approach for analog circuits. In Southwest Symposium on Mixed-Signal Design.Google Scholar
- A. Vashist, A. Ganguly, and M. Indovina. 2018. Testing WiNoC-enabled multicore chips with BIST for wireless interconnects. In IEEE/ACM International Symposium on Networks-on-Chip (NOCS).Google Scholar
- A. Vashist, A. Keats, Sai Manoj P. D., and A. Ganguly. 2019. Securing a wireless network-on-chip against jamming based denial-of-service and eavesdropping attacks. IEEE Transactions on Very Large Scale Integration Systems (TVLSI) (2019).Google Scholar
- A. Vashist, A. Keats, Sai Manoj P. D., and A. Ganguly. 2019. Securing a wireless network-on-chip against jamming based denial-of-service attacks. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI).Google Scholar
- B. Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas. 2003. Bringing communication networks on a chip: Test and verification implications. IEEE Communications Magazine 41, 9 (Sep 2003), 74--81.Google ScholarDigital Library
- X. Wang, Y. Zheng, A. Basak, and S. Bhunia. 2015. IIPS: Infrastructure IP for secure SoC design. IEEE Trans. Comput. 64, 8 (Aug 2015), 2226--2238.Google ScholarDigital Library
- T. W. Williams and W. Daehn. 1989. Aliasing errors in multiple input signature analysis registers. In European Test Conference.Google Scholar
- Bing Wu, Jianmin Chen, Jie Wu, and Mihaela Cardei. 2007. A Survey of Attacks and Countermeasures in Mobile Ad Hoc Networks. Springer US, 103--135.Google Scholar
- S. S. Wu, K. Wang, Sai Manoj P. D., T. Y. Ho, M. Yu, and H. Yu. 2014. A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os. In Design, Automation Test in Europe Conference Exhibition (DATE).Google Scholar
- X. Yu, H. Rashtian, S. Mirabbasi, P. P. Pande, and D. Heo. 2015. An 18.7-Gb/s 60-GHz OOK demodulator in 65-nm CMOS for wireless network-on-chip. IEEE Trans. on Circuits and Systems I 62, 3 (March 2015), 799--806.Google Scholar
- X. Yu, S. P. Sah, H. Rashtian, S. Mirabbasi, P. P. Pande, and D. Heo. 2014. A 1.2-pJ/bit 16-Gb/s 60-GHz OOK transmitter in 65-nm CMOS for wireless network-on-chip. IEEE Trans. on Microwave Theory and Tech. 62, 10 (Oct 2014), 2357--2369.Google ScholarCross Ref
- M. Zekri, S. E. Kafhali, N. Aboutabit, and Y. Saadi. 2017. DDoS attack detection using machine learning techniques in cloud computing environments. In Int. Conf. of Cloud Computing Technologies and Applications (CloudTech).Google Scholar
- D. Zhao, S. Upadhyaya, and M. Margala. 2006. Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 7 (July 2006), 1411--1418.Google ScholarDigital Library
- D. Zhao and Y. Wang. 2006. MTNET: Design and optimization of a wireless SOC test framework. In IEEE International SOC Conference.Google Scholar
Index Terms
- Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips
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