Yuzhe Ma
ABSTRACT
As the scale of integrated circuits keeps increasing, it is witnessed that there is a surge in the research of electronic design automation (EDA) to make the technology node scaling happen. Graph is of great significance in the technology evolution since it is one of the most natural ways of abstraction to many fundamental objects in EDA problems like netlist and layout, and hence many EDA problems are essentially graph problems. Traditional approaches for solving these problems are mostly based on analytical solutions or heuristic algorithms, which require substantial efforts in designing and tuning. With the emergence of the learning techniques, dealing with graph problems with machine learning or deep learning has become a potential way to further improve the quality of solutions. In this paper, we discuss a set of key techniques for conducting machine learning on graphs. Particularly, a few challenges in applying graph learning to EDA applications are highlighted. Furthermore, two case studies are presented to demonstrate the potential of graph learning on EDA applications.
- K.-C. Chen, J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar, “Dag-map: Graph-based fpga technology mapping for delay optimization,” IEEE Design & Test of Computers, vol. 9, no. 3, pp. 7--20, 1992.Google Scholar
Digital Library
- K.-T. Cheng and C.-J. Lin, “Timing-driven test point insertion for full-scan and partial-scan BIST,” in Proc. ITC, 1995, pp. 506--514.Google Scholar
- N. Selvakkumaran and G. Karypis, “Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization,” IEEE TCAD, vol. 25, no. 3, pp. 504--517, 2006.Google ScholarDigital Library
- B. Hu and M. Marek-Sadowska, “Fine granularity clustering-based placement,” IEEE TCAD, vol. 23, no. 4, pp. 527--536, april 2004.Google Scholar
- A. B. Kahng, C.-H. Park, X. Xu, and H. Yao, “Layout decomposition approaches for double patterning lithography,” IEEE TCAD, vol. 29, pp. 939--952, June 2010.Google ScholarDigital Library
- B. Yu, K. Yuan, D. Ding, and D. Z. Pan, “Layout decomposition for triple patterning lithography,” IEEE TCAD, vol. 34, no. 3, pp. 433--446, March 2015.Google ScholarCross Ref
- D. Z. Pan, B. Yu, and J.-R. Gao, “Design for manufacturing with emerging nanolithography,” IEEE TCAD, vol. 32, no. 10, pp. 1453--1472, 2013.Google ScholarDigital Library
- M. Cho and D. Z. Pan, “BoxRouter: a new global router based on box expansion and progressive ILP,” in Proc. DAC, 2006, pp. 373--378.Google ScholarDigital Library
- Y. Lin, B. Yu, X. Xu, J.-R. Gao, N. Viswanathan, W.-H. Liu, Z. Li, C. J. Alpert, and D. Z. Pan, “MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes,” IEEE TCAD, 2017.Google Scholar
- H. Li, W.-K. Chow, G. Chen, E. F. Young, and B. Yu, “Routability-driven and fence-aware legalization for mixed-cell-height circuits,” in Proc. DAC, 2018, pp. 1--6.Google Scholar
- G. Chen and E. F. Young, “Salt: provably good routing topology by a novel steiner shallow-light tree algorithm,” IEEE TCAD, 2019.Google ScholarCross Ref
- S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen, “A novel layout decomposition algorithm for triple patterning lithography,” IEEE TCAD, vol. 33, no. 3, pp. 397--408, March 2014.Google ScholarDigital Library
- H. Zhang, B. Yu, and E. F. Y. Young, “Enabling online learning in lithography hotspot detection with information-theoretic feature optimization,” in Proc. ICCAD, 2016, pp. 47:1--47:8.Google ScholarDigital Library
- H. Geng, W. Zhong, H. Yang, Y. Ma, J. Mitra, and B. Yu, “Sraf insertion via supervised dictionary learning,” IEEE TCAD, 2019.Google ScholarDigital Library
- W.-H. Chang, L.-D. Chen, C.-H. Lin, S.-P. Mu, M. C.-T. Chao, C.-H. Tsai, and Y.-C. Chiu, “Generating routing-driven power distribution networks with machine-learning technique,” in Proc. ISPD, 2016, pp. 145--152.Google ScholarDigital Library
- Y. Ma, S. Roy, J. Miao, J. Chen, and B. Yu, “Cross-layer optimization for high speed adders: A pareto driven machine learning approach,” IEEE TCAD, vol. 38, no. 12, pp. 2298--2311, 2018.Google Scholar
- C.-W. Pui, G. Chen, Y. Ma, E. F. Young, and B. Yu, “Clock-aware ultrascale fpga placement with machine learning routability prediction,” in Proc. ICCAD, 2017, pp. 929--936.Google ScholarCross Ref
- H. Yang, S. Li, Y. Ma, B. Yu, and E. F. Young, “GAN-OPC: Mask optimization with lithography-guided generative adversarial nets,” in Proc. DAC, 2018, pp. 131:1--131:6.Google ScholarDigital Library
- H. Yang, J. Su, Y. Zou, Y. Ma, B. Yu, and E. F. Y. Young, “Layout hotspot detection with feature tensor generation and deep biased learning,” IEEE TCAD, 2018.Google Scholar
- Z. Xie, Y.-H. Huang, G.-Q. Fang, H. Ren, S.-Y. Fang, Y. Chen, and J. Hu, “RouteNet: Routability prediction for mixed-size designs using convolutional neural network,” in Proc. ICCAD, 2018, pp. 80:1--80:8.Google ScholarDigital Library
- T. N. Kipf and M. Welling, “Semi-supervised classification with graph convolutional networks,” Proc. ICLR, 2016.Google Scholar
- W. Hamilton, Z. Ying, and J. Leskovec, “Inductive representation learning on large graphs,” in Proc. NIPS, 2017, pp. 1024--1034.Google Scholar
- R. Ying, R. He, K. Chen, P. Eksombatchai, W. L. Hamilton, and J. Leskovec, “Graph convolutional neural networks for web-scale recommender systems,” in Proc. KDD, 2018, pp. 974--983.Google ScholarDigital Library
- D. Xu, Y. Zhu, C. B. Choy, and L. Fei-Fei, “Scene graph generation by iterative message passing,” in Proc. CVPR, 2017, pp. 5410--5419.Google ScholarCross Ref
- J. You, B. Liu, Z. Ying, V. Pande, and J. Leskovec, “Graph convolutional policy network for goal-directed molecular graph generation,” in Proc. NIPS, 2018, pp. 6410--6421.Google Scholar
- J. You, R. Ying, X. Ren, W. Hamilton, and J. Leskovec, “Graphrnn: Generating realistic graphs with deep auto-regressive models,” in Proc. ICML, 2018, pp. 5694--5703.Google Scholar
- H. Dai, H. Li, T. Tian, X. Huang, L. Wang, J. Zhu, and L. Song, “Adversarial attack on graph structured data,” in Proc. ICML, 2018, pp. 1123--1132.Google Scholar
- Y. Ma, H. Ren, B. Khailany, H. Sikka, L. Luo, K. Natarajan, and B. Yu, “High performance graph convolutional networks with applications in testability analysis,” in Proc. DAC, 2019, p. 18.Google ScholarDigital Library
- R. J. Francis, J. Rose, and K. Chung, “Chortle: A technology mapping program for lookup table-based field programmable gate arrays,” in Proc. DAC, 1990, pp. 613--619.Google ScholarDigital Library
- R. Brayton and A. Mishchenko, “Abc: An academic industrial-strength verification tool,” in International Conference on Computer Aided Verification, 2010, pp. 24--40.Google ScholarDigital Library
- C. J. Alpert, A. E. Caldwell, A. B. Kahng, and I. L. Markov, “Hypergraph partitioning with fixed vertices,” IEEE TCAD, vol. 19, no. 2, pp. 267--272, 2000.Google Scholar
- B. Yu, X. Xu, J.-R. Gao, Y. Lin, Z. Li, C. Alpert, and D. Z. Pan, “Methodology for standard cell compliance and detailed placement for triple patterning lithography,” IEEE TCAD, vol. 34, no. 5, pp. 726--739, May 2015.Google ScholarCross Ref
- R. E. Bryant, “Graph-based algorithms for boolean function manipulation,” IEEE TC, vol. 100, no. 8, pp. 677--691, 1986.Google ScholarDigital Library
- J. Cong and P. H. Madden, “Performance driven global routing for standard cell design,” in Proc. ISPD, vol. 14, no. 16, 1997, pp. 73--80.Google Scholar
- C. Albrecht, “Provably good global routing by a new approximation algorithm for multicommodity flow,” in Proc. ISPD, 2000, pp. 19--25.Google ScholarDigital Library
- T. Yoshimura and E. S. Kuh, “Efficient algorithms for channel routing,” IEEE TCAD, vol. 1, no. 1, pp. 25--35, 1982.Google Scholar
- K. Yuan, J.-S. Yang, and D. Z. Pan, “Double patterning layout decomposition for simultaneous conflict and stitch minimization,” IEEE TCAD, vol. 29, no. 2, pp. 185--196, Feb. 2010.Google ScholarDigital Library
- H.-Y. Chang and I. H.-R. Jiang, “Multiple patterning layout decomposition considering complex coloring rules,” in Proc. DAC, 2016, pp. 40:1--40:6.Google ScholarDigital Library
- Y. Ma, J.-R. Gao, J. Kuang, J. Miao, and B. Yu, “A unified framework for simultaneous layout decomposition and mask optimization,” in Proc. ICCAD, 2017, pp. 81--88.Google ScholarCross Ref
- R. Bellman, “On a routing problem,” Quarterly of applied mathematics, vol. 16, no. 1, pp. 87--90, 1958.Google ScholarCross Ref
- L.-T. Wang, Y.-W. Chang, and K.-T. T. Cheng, Electronic design automation: synthesis, verification, and test. hskip 1em plus 0.5em minus 0.4emrelax Morgan Kaufmann, 2009.Google Scholar
- B. Yu and D. Z. Pan, “Layout decomposition for quadruple patterning lithography and beyond,” in Proc. DAC, 2014, pp. 53:1--53:6.Google Scholar
- B. Yu, Y.-H. Lin, G. Luk-Pat, D. Ding, K. Lucas, and D. Z. Pan, “A high-performance triple patterning layout decomposer with balanced density,” in Proc. ICCAD, 2013, pp. 163--169.Google ScholarCross Ref
- C. K. Cheng, S. Z. Yao, and T. C. Hu, “The orientation of modules based on graph decomposition,” IEEE TC, vol. 40, pp. 774--780, June 1991.Google ScholarDigital Library
- C.-W. Sham, F. Y. Young, and C. Chu, “Optimal cell flipping in placement and floorplanning,” in Proc. DAC, 2006, pp. 1109--1114.Google ScholarDigital Library
- J. Kuang and E. F. Y. Young, “An efficient layout decomposition approach for triple patterning lithography,” in Proc. DAC, 2013, pp. 69:1--69:6.Google ScholarDigital Library
- Y. Yang, W.-S. Luk, D. Z. Pan, H. Zhou, C. Yan, D. Zhou, and X. Zeng, “Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography,” IEEE TCAD, vol. 35, no. 9, pp. 1532--1545, 2016.Google Scholar
- M. Cho and D. Z. Pan, “BoxRouter: a new global router based on box expansion and progressive ILP,” IEEE TCAD, vol. 26, no. 12, pp. 2130--2143, 2007.Google Scholar
- Y. Lin, X. Xu, B. Yu, R. Baldick, and D. Z. Pan, “Triple/quadruple patterning layout decomposition via linear programming and iterative rounding,” JM3, vol. 16, no. 2, 2017.Google Scholar
- R. Samanta, J. Hu, and P. Li, “Discrete buffer and wire sizing for link-based non-tree clock networks,” IEEE TVLSI, vol. 18, no. 7, pp. 1025--1035, 2009.Google Scholar
- A. B. Kahng, S. Kang, H. Lee, S. Nath, and J. Wadhwani, “Learning-based approximation of interconnect delay and slew in signoff timing tools,” in Proc. SLIP, 2013, pp. 1--8.Google ScholarCross Ref
- W.-T. J. Chan, K. Y. Chung, A. B. Kahng, N. D. MacDonald, and S. Nath, “Learning-based prediction of embedded memory timing failures during initial floorplan design,” in Proc. ASPDAC, 2016, pp. 178--185.Google ScholarDigital Library
- Z. Qi, Y. Cai, and Q. Zhou, “Accurate prediction of detailed routing congestion using supervised data learning,” in Proc. ICCD, 2014, pp. 97--103.Google ScholarCross Ref
- Q. Zhou, X. Wang, Z. Qi, Z. Chen, Q. Zhou, and Y. Cai, “An accurate detailed routing routability prediction model in placement,” in Proc. ASQED, 2015, pp. 119--122.Google ScholarCross Ref
- H. Cai, V. W. Zheng, and K. Chang, “A comprehensive survey of graph embedding: problems, techniques and applications,” IEEE TKDE, vol. 30, no. 9, pp. 1616--1637, 2018.Google Scholar
- Z. Wu, S. Pan, F. Chen, G. Long, C. Zhang, and P. S. Yu, “A comprehensive survey on graph neural networks,” arXiv preprint arXiv:1901.00596, 2019.Google Scholar
- J. Bruna, W. Zaremba, A. Szlam, and Y. LeCun, “Spectral networks and locally connected networks on graphs,” arXiv preprint arXiv:1312.6203, 2013.Google Scholar
- M. Defferrard, X. Bresson, and P. Vandergheynst, “Convolutional neural networks on graphs with fast localized spectral filtering,” in Advances in neural information processing systems, 2016, pp. 3844--3852.Google ScholarDigital Library
- A. Micheli, “Neural network for graphs: A contextual constructive approach,” IEEE Transactions on Neural Networks, vol. 20, no. 3, pp. 498--511, 2009.Google ScholarDigital Library
- J. Atwood and D. Towsley, “Diffusion-convolutional neural networks,” in Advances in Neural Information Processing Systems, 2016, pp. 1993--2001.Google Scholar
- P. Velivc ković, G. Cucurull, A. Casanova, A. Romero, P. Lio, and Y. Bengio, “Graph attention networks,” arXiv preprint arXiv:1710.10903, 2017.Google Scholar
- A. Bojchevski, J. Klicpera, B. Perozzi, M. Blais, A. Kapoor, M. Lukasik, and S. Günnemann, “Is pagerank all you need for scalable graph neural networks?” 2019.Google Scholar
- R. Ying, R. He, K. Chen, P. Eksombatchai, W. L. Hamilton, and J. Leskovec, “Graph convolutional neural networks for web-scale recommender systems,” in Proceedings of the 24th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining. hskip 1em plus 0.5em minus 0.4emrelax ACM, 2018, pp. 974--983.Google ScholarDigital Library
- C. Deng, Z. Zhao, Y. Wang, Z. Zhang, and Z. Feng, “Graphzoom: A multi-level spectral approach for accurate and scalable graph embedding,” arXiv preprint arXiv:1910.02370, 2019.Google Scholar
- M. Wang, L. Yu, D. Zheng, Q. Gan, Y. Gai, Z. Ye, M. Li, J. Zhou, Q. Huang, C. Ma et al., “Deep graph library: Towards efficient and scalable deep learning on graphs,” arXiv preprint arXiv:1909.01315, 2019.Google Scholar
- Y. Feng, H. You, Z. Zhang, R. Ji, and Y. Gao, “Hypergraph neural networks,” in Proc. AAAI, vol. 33, 2019, pp. 3558--3565.Google ScholarCross Ref
- S. Bai, F. Zhang, and P. H. Torr, “Hypergraph convolution and hypergraph attention,” arXiv preprint arXiv:1901.08150, 2019.Google Scholar
- N. Yadati, M. Nimishakavi, P. Yadav, V. Nitin, A. Louis, and P. Talukdar, “Hypergcn: A new method for training graph convolutional networks on hypergraphs,” in Advances in Neural Information Processing Systems, 2019, pp. 1509--1520.Google Scholar
- T.-H. H. Chan and Z. Liang, “Generalizing the hypergraph laplacian via a diffusion process with mediators,” Theoretical Computer Science, 2019.Google Scholar
- C. Zhang, D. Song, C. Huang, A. Swami, and N. V. Chawla, “Heterogeneous graph neural network,” in Proc. KDD. hskip 1em plus 0.5em minus 0.4emrelax ACM, 2019, pp. 793--803.Google ScholarDigital Library
- M. Schlichtkrull, T. N. Kipf, P. Bloem, R. Van Den Berg, I. Titov, and M. Welling, “Modeling relational data with graph convolutional networks,” in European Semantic Web Conference. hskip 1em plus 0.5em minus 0.4emrelax Springer, 2018, pp. 593--607.Google ScholarCross Ref
- X. Wang, H. Ji, C. Shi, B. Wang, Y. Ye, P. Cui, and P. S. Yu, “Heterogeneous graph attention network.”hskip 1em plus 0.5em minus 0.4emrelax ACM, 2019, pp. 2022--2032.Google Scholar
- S. Yun, M. Jeong, R. Kim, J. Kang, and H. J. Kim, “Graph transformer networks,” in Proc. NIPS, 2019, pp. 11,960--11,970.Google Scholar
- L. H. Goldstein and E. L. Thigpen, “SCOAP: Sandia controllability/observability analysis program,” in Proc. DAC, 1980, pp. 190--196.Google ScholarDigital Library
- L. v. d. Maaten and G. Hinton, “Visualizing data using t-SNE,” Journal of Machine Learning Research, vol. 9, no. Nov, pp. 2579--2605, 2008.Google ScholarDigital Library
Index Terms
- Understanding Graphs in EDA: From Shallow to Deep Learning
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