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An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept

Published:29 January 2021Publication History

ABSTRACT

This paper presents a wide-dynamic-range high-resolution time-domain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept allows a virtual delay line extension and is applied to achieve high resolution down to 1ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1ns to 12 ns allow on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. The concept of this paper is evaluated by a custom-designed FPGA supported PCB. The presented concept is highly suitable for on-chip integration.

University LSI Design Contest ASP-DAC 2021

References

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  1. An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept

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          • Published in

            cover image ACM Conferences
            ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference
            January 2021
            930 pages
            ISBN:9781450379991
            DOI:10.1145/3394885

            Copyright © 2021 ACM

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            Publication History

            • Published: 29 January 2021

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            Acceptance Rates

            ASPDAC '21 Paper Acceptance Rate111of368submissions,30%Overall Acceptance Rate466of1,454submissions,32%

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