Hao Yu Chi
Abstract
As design complexity is increased exponentially, electronic design automation (EDA) tools are essential to reduce design efforts. However, the analog layout design has still been done manually for decades because it is a sensitive and error-prone task. Tool-generated layouts are still not well-accepted by analog designers due to the performance loss under non-ideal effects. Most previous works focus on adding more layout constraints on the analog placement. Routing the nets is thus considered as a trivial step that can be done by typical digital routing methodology, which is to use vias to connect every horizontal and vertical lines. Those extra vias will significantly increase the wire loads and degrade the circuit performance. Therefore, in this article, a wire load oriented analog routing methodology is proposed to reduce the number of layer changing of each routing net. Wire load is considered in the optimization goal as well as the wire length to keep the circuit performance after layout, while the analog layout constraints like symmetry and length matching are still satisfied during routing. As shown in the experimental results, this approach significantly reduces the wire load and performance loss after layout with little overhead on wire length.
- C.-C. Chang and J. J. S. Cong. 1999. An efficient approach to multilayer layer assignment with an application to via minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, 5 (May 1999), 605--620.Google Scholar
- H.-Y. Chi, H.-Y. Tseng, C.-N. Jimmy Liu, and H.-M. Chen. 2018. Performance-preserved analog routing methodology via wire load reduction. In IEEE/ACM Proceedings of Asia and South Pacific Design Automation Conference.Google ScholarCross Ref
- P.-Y. Chou, H.-C. Ou, and Y.-W. Chang. 2011. Heterogeneous b*-trees for analog placement with symmetry and regularity considerations. In IEEE/ACM Proceedings of International Conference on Computer-Aided Design. 512--516.Google Scholar
- C. Chu and Y.-C. Wong. 2008. FLUTE: Fast lookup table based rectilinear steiner minimal tree algorithm for VLSI design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, 1 (Jan 2008), 70--83.Google ScholarDigital Library
- J. M. Cohn, D. J. Garrod, R. A. Rutenbar, and L. R. Carley. 1991. KOAN/ANAGRAM II: New tools for device-level analog placement and routing. IEEE Journal of Solid-State Circuits 26, 3 (Mar 1991), 330--342.Google ScholarCross Ref
- C. Du, Y. Cai, and X. Hong. 2006. A novel analog routing algorithm with constraints of variable wire widths. In IEEE Proceedings of International Conference on Communications, Circuits and Systems.Google Scholar
- Q. Gao, H. Yao, Q. Zhou, and Y. Cai. 2011. A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. In IEEE Proceedings of International Symposium on Quality Electronic Design.Google Scholar
- H. E. Graeb. 2010. Analog Layout Synthesis: A Survey of Topological Approaches. Springer, Berlin.Google Scholar
- M.-K. Hsu, S. Chou, T.-H. Lin, and Y.-W. Chang. 2011. Routability-driven analytical placement for mixed-size circuit designs. In IEEE/ACM Proceedings of International Conference on Computer-Aided Design. 6.Google ScholarDigital Library
- Lee. 1961. An algorithm for path connection and its application. IRE Transactions on Electronic Computer (1961).Google Scholar
- C.-W. Lin, C.-C. Lu, J.-M. Lin, and S.-J. Chang. 2012. Routability-driven placement algorithm for analog integrated circuits. In ACM Proceedings of International Symposium on Physical Design. 71--78.Google ScholarDigital Library
- P.-H. Lin, Y.-W. Chang, and S.-C. Lin. 2009. Analog placement based on symmetry-island formulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 6 (Jun 2009), 791--804.Google Scholar
- E. Malavasi, E. Charbon, E. Felt, and A. S.-Vincentelli. 1996. Automation of IC layout with analog constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15, 8 (Aug 1996), 1186--1197.Google ScholarDigital Library
- E. Malavasi, M. Chilanti, and R. Guerrieri. 1989. A general router for analog layout. In IEEE Proceedings of CompEuro Computers in Design Manufacturing and Production.Google Scholar
- E. Malavasi and A. S.-Vincentelli. 1993. Area routing for analog layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, 8 (Aug 1993), 1186--1197.Google ScholarDigital Library
- H.-C. Ou, H.-C. C. Chien, and Y.-W. Chang. 2012. Non-uniform multilevel analog routing with matching constraints. In IEEE/ACM Proceedings of Design Automation Conference. 549--554.Google ScholarDigital Library
- M. Ozdal and R. Hentschke. 2014. Algorithms for maze routing with exact matching constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, 1 (Jan 2014), 101--112.Google ScholarDigital Library
- A. Patyal, P.-C. Pan, A. K A, H.-M. Chen, H.-Y. Chi, and C.-N. Jimmy Liu. 2018. Analog placement with current flow and symmetry constraints using PCP-CP. In IEEE/ACM Proceedings of Design Automation Conference.Google Scholar
- R. A. Rutenbar, G. G. E. Gielen, and J. Roychowdhury. 2007. Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs. In IEEE Proceedings of IEEE. 640--669.Google Scholar
- K. Sajid, J. D. Carothers, J. J. Rodriguez, and W. T. Holman. 2001. Global routing methodology for analog and mixed-signal layout. In IEEE Proceedings of ASIC/SOC.Google Scholar
- M. Torabi and L. Zhang. 2018. Electromigration- and parasitic-aware ILP-based analog router. IEEE Transactions on Very Large Scale Integration (VLSI) System 26, 10 (June 2018), 1854--1867.Google ScholarCross Ref
- Y.-P. Weng, H.-M. Chen, T.-C. Chen, P.-C. Pan, C.-H. Chen, and W.-Z. Chen. 2011. Fast analog layout prototyping for nanometer design migration. In IEEE/ACM Proceedings of International Conference on Computer-Aided Design. 517--522.Google ScholarDigital Library
- C.-Y. Wu, H. Graeb, and J. Hu. 2015. A pre-search assisted ILP approach to analog integrated circuit routing. In IEEE/ACM Proceedings of International Conference on Computer Design.Google Scholar
- L. Xiao, E. F.-Y. Young, X. He, and K.-P. Pun. 2010. Practical placement and routing techniques for analog circuit designs. In IEEE/ACM Proceedings of International Conference on Computer-Aided Design. 675--679.Google ScholarDigital Library
- H. Yao, Y. Cai, and Q. Gao. 2012. LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. In IEEE/ACM Proceedings of Asia and South Pacific Design Automation Conference. 157--162.Google Scholar
- L. Zhang, U. Kleine, and Y. Jiang. 2006. An automated design tool for analog layouts. IEEE Transactions on Very Large Scale Integration Systems 14, 8 (Aug 2006), 881--894.Google Scholar
- V. M. zu Bexten, C. Moraga, R. Klinke, W. Brockherde, and K.-G. Hess. 1993. ALSYN: Flexible rule-based layout synthesis for analog ICs. IEEE Journal of Solid-State Circuits 28, 3 (Mar 1993), 261--168.Google Scholar
Index Terms
- Wire Load Oriented Analog Routing with Matching Constraints
Recommendations
Non-uniform multilevel analog routing with matching constraints
DAC '12: Proceedings of the 49th Annual Design Automation ConferenceSymmetry, topology-matching, and length-matching constraints are three major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. ...
OptiPlace: optimized placement solution for mixed-size designs
AbstractIn this paper, an optimized placement approach has been presented for mixed-size designs. A novel initial placement approach is introduced to achieve routability-aware global placement using new routability-aware cell clustering, cluster ...
Performance-preserved analog routing methodology via wire load reduction
ASPDAC '18: Proceedings of the 23rd Asia and South Pacific Design Automation ConferenceAnalog layout automation is a popular research direction in recent years to raise the design productivity. However, the research on this topic is still not well accepted by analog designers because notable performance loss often exists in tool-generated ...
Comments