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CLU: A Near-Memory Accelerator Exploiting the Parallelism in Convolutional Neural Networks

Published:15 April 2021Publication History
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Abstract

Convolutional/Deep Neural Networks (CNNs/DNNs) are rapidly growing workloads for the emerging AI-based systems. The gap between the processing speed and the memory-access latency in multi-core systems affects the performance and energy efficiency of the CNN/DNN tasks. This article aims to alleviate this gap by providing a simple and yet efficient near-memory accelerator-based system that expedites the CNN inference. Towards this goal, we first design an efficient parallel algorithm to accelerate CNN/DNN tasks. The data is partitioned across the multiple memory channels (vaults) to assist in the execution of the parallel algorithm. Second, we design a hardware unit, namely the convolutional logic unit (CLU), which implements the parallel algorithm. To optimize the inference, the CLU is designed, and it works in three phases for layer-wise processing of data. Last, to harness the benefits of near-memory processing (NMP), we integrate homogeneous CLUs on the logic layer of the 3D memory, specifically the Hybrid Memory Cube (HMC). The combined effect of these results in a high-performing and energy-efficient system for CNNs/DNNs. The proposed system achieves a substantial gain in the performance and energy reduction compared to multi-core CPU- and GPU-based systems with a minimal area overhead of 2.37%.

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        cover image ACM Journal on Emerging Technologies in Computing Systems
        ACM Journal on Emerging Technologies in Computing Systems  Volume 17, Issue 2
        Hardware and Algorithms for Efficient Machine Learning
        April 2021
        360 pages
        ISSN:1550-4832
        EISSN:1550-4840
        DOI:10.1145/3446841
        • Editor:
        • Ramesh Karri
        Issue’s Table of Contents

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        Publication History

        • Published: 15 April 2021
        • Accepted: 1 September 2020
        • Revised: 1 August 2020
        • Received: 1 May 2020
        Published in jetc Volume 17, Issue 2

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