ABSTRACT
Verifying the functional correctness of a circuit is often the most time-consuming part of the design process. Recently, world-level formal verification methods, e.g., Binary Moment Diagram (BMD) and Symbolic Computer Algebra (SCA) have reported very good results for proving the correctness of arithmetic circuits. However, these techniques still frequently fail due to memory or time requirements. The unknown complexity bounds of these techniques make it impossible to predict before invoking the verification tool whether it will successfully terminate or run for an indefinite amount of time.
In this paper, we formally prove that for integer arithmetic circuits, the entire verification process requires at most linear space and quadratic time with respect to the size of the circuit function. This is shown for the two main word-level verification methods: backward construction using BMD and backward substitution using SCA. We support the architectures which are used in the implementation of integer polynomial operations, e.g., X3 - XY2 + XY. Finally, we show in practice that the required space and run times of the word-level methods match the predicted results in theory when it comes to the verification of different arithmetic circuits, including exponentiation circuits with different power values (XP : 2 ≤ P ≤ 7) and more complicated circuits (e.g., X2 + XY + X).
- 2018. ABC: A System for Sequential Synthesis and Verification. available at https://people.eecs.berkeley.edu/~alanmi/abc/.Google Scholar
- Randal E. Bryant. 1995. Binary decision diagrams and beyond: enabling technologies for formal verification. In International Conference on Computer-Aided Design. 236--243.Google ScholarCross Ref
- David A. Cox, John Little, and Donal O'Shea. 1997. Ideals Varieties and Algorithms. Springer.Google Scholar
- David John Dempster and Michael George Stuart. 2001. Verification Methodology Manual - Techniques for Verifying HDL Designs. Teamwork International.Google Scholar
- Stefan Disch and Christoph Scholl. 2007. Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets. In ASP Design Automation Conf. 938--943.Google ScholarDigital Library
- Rolf Drechsler. 2021. PolyAdd: Polynomial Formal Verification of Adder Circuits. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. 99--104.Google Scholar
- Rolf Drechsler. 2021. Polynomial Circuit Verification using BDDs. arXiv:2104.03024.Google Scholar
- Rolf Drechsler and Bernd Becker. 1998. Binary Decision Diagrams - Theory and Implementation. Kluwer Academic Publishers.Google Scholar
- Rolf Drechsler and Caroline Dominik. 2021. Edge Verification: Ensuring Correctness under Resource Constraints. In Symposium on Integrated Circuits and System Design.Google ScholarCross Ref
- Rolf Drechsler, Alireza Mahzoon, and Lennart Weingarten. 2021. Polynomial Formal Verification of Arithmetic Circuits. In International Conference on Computational Intelligence and Data Engineering.Google Scholar
- Reinhard Enders. 1995. Note on the complexity of binary moment diagram representations. In Int'l Workshop on Applications of the Reed-Muller Expansion in Circuit Design. 191--197.Google Scholar
- Farimah Farahmandi and Bijan Alizadeh. 2015. Gröbner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction. Microprocessors and Microsystems 39, 2 (2015), 83--96.Google ScholarDigital Library
- Evguenii I. Goldberg, Mukul R. Prasad, and Robert K. Brayton. 2001. Using SAT for combinational equivalence checking. In Design, Automation and Test in Europe. 114--121.Google Scholar
- Kiyoharu Hamaguchi, Akihito Morita, and Shuzo Yajima. 1995. Efficient Construction of Binary Moment Diagrams for Verifying Arithmetic Circuits. In International Conference on Computer-Aided Design. 78--82.Google Scholar
- Deepak Kapur and Mahadevan Subramaniam. 1998. Mechanical Verification of Adder Circuits using Rewrite Rule Laboratory. Formal Methods in System Design 13, 2 (1998), 127--158.Google ScholarDigital Library
- Daniela Kaufmann, Armin Biere, and Manuel Kauers. 2019. Verifying Large Multipliers by Combining SAT and Computer Algebra. In Int'l Conf. on Formal Methods in CAD. 28--36.Google Scholar
- Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, and Paul Molitor. 2003. Polynomial Formal Verification of Multipliers. Formal Meth. in Sys. Des. 22, 1 (2003), 39--58.Google ScholarDigital Library
- Robert P. Kurshan and Leslie Lamport. 1993. Verification of a multiplier: 64 bits and beyond. In Computer Aided Verification. 166--179.Google Scholar
- Alireza Mahzoon and Rolf Drechsler. 2021. Late Breaking Results: Polynomial Formal Verification of Fast Adders. In Design Automation Conf.Google Scholar
- Alireza Mahzoon and Rolf Drechsler. 2021. Polynomial Formal Verification of Prefix Adders. In Asian Test Symp.Google Scholar
- Alireza Mahzoon, Daniel Große, and Rolf Drechsler. 2018. PolyCleaner: Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers. In International Conference on Computer-Aided Design. 129:1--129:8.Google ScholarDigital Library
- Alireza Mahzoon, Daniel Große, and Rolf Drechsler. 2019. RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. In Design Automation Conf. 185:1--185:6.Google ScholarDigital Library
- Alireza Mahzoon, Daniel Große, and Rolf Drechsler. 2021. REVSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2021).Google ScholarCross Ref
- Alireza Mahzoon, Daniel Große, Christoph Scholl, and Rolf Drechsler. 2020. Towards Formal Verification of Optimized and Industrial Multipliers. In Design, Automation and Test in Europe. 544--549.Google Scholar
- Lloris Ruiz, Castillo Morales, Parrilla Roure, and García Ríos. 2014. Algebraic Circuits. Springer.Google Scholar
- Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, and Jacob A. Abraham. 2007. Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. on Comp. 56, 10 (2007), 1401--1414.Google ScholarDigital Library
- Cunxi Yu, Walter Brown, Duo Liu, Andre Rossi, and Maciej Ciesielski. 2016. Formal verification of arithmetic circuits by function extraction. IEEE Transactions on Computer Aided Design of Circuits and Systems 35, 12 (2016), 2131--2142.Google ScholarDigital Library
- Cunxi Yu, Maciej Ciesielski, and Alan Mishchenko. 2017. Fast Algebraic Rewriting Based on And-Inverter Graphs. IEEE Transactions on Computer Aided Design of Circuits and Systems 37, 9 (2017), 1907--1911.Google ScholarDigital Library
Index Terms
- Polynomial word-level verification of arithmetic circuits
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