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Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasures

Published:23 August 2022Publication History

ABSTRACT

In this paper, we propose a novel class of speculative attacks, called Timed Speculative Attacks (TSA), that does not depend on the state changes in the cache memory. Instead, it makes use of the timing differences that occur due to store-to-load forwarding. We propose two attack strategies - Fill-and-Forward utilizing correctly speculated loads, and Fill-and-Misdirect using mis-speculated load instructions. While Fill-and-Forward exploits the shared store buffers in a multi-threaded CPU core, the Fill-and-Misdirect approach exploits the influence of rolled back mis-speculated loads on subsequent instructions. As case studies, we demonstrate a covert channel using Fill-and-Forward and key recovery attacks on OpenSSL AES and Romulus-N Authenticated Encryption with Associated Data scheme using Fill-and-Misdirect approach. Finally, we show that TSA is able to subvert popular cache-based countermeasures for transient attacks.

References

  1. G. Abraham et al. 2018. Spectrum : Classifying, Replicating and Mitigating Spectre Attacks on a Speculating RISC-V Microarchitecture.Google ScholarGoogle Scholar
  2. S. Ainsworth et al. 2020. MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State. In ISCA, 2020.Google ScholarGoogle Scholar
  3. K. Barber et al. 2019. SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels. In PACT, 2019.Google ScholarGoogle ScholarCross RefCross Ref
  4. K. Basu et al. 2020. A Theoretical Study of Hardware Performance Counters-Based Malware Detection. IEEE Trans. Inf. Forensics Secur., 2020 (2020).Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. A. Bhattacharyya et al. 2019. SMoTherSpectre: Exploiting Speculative Execution through Port Contention. In ACM SIGSAC, CCS, 2019.Google ScholarGoogle Scholar
  6. J. V. Bulck et al. 2020. LVI: Hijacking Transient Execution through Microarchitectural Load Value Injection. In IEEE S&P 2020.Google ScholarGoogle Scholar
  7. C. Canella et al. 2019. Fallout: Leaking Data on Meltdown-resistant CPUs. In ACM SIGSAC, CCS, 2019.Google ScholarGoogle Scholar
  8. J. Fustos et al. 2019. SpectreGuard: An Efficient Data-centric Defense Mechanism against Spectre Attacks. In DAC, 2019.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Qian Ge et al. 2018. A Survey of Micro-architectural Timing Attacks and Countermeasures on Contemporary Hardware. JCE (2018).Google ScholarGoogle Scholar
  10. C. Guo et al. 2021. Romulus Specification v1.3.Google ScholarGoogle Scholar
  11. Saad Islam et al. 2019. SPOILER: Speculative Load Hazards Boost Rowhammer and Cache Attacks. In USENIX Security 2019.Google ScholarGoogle Scholar
  12. Khaled N. K. et al. 2019. SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation (DAC, 2019).Google ScholarGoogle Scholar
  13. Abdul Kadir et al. 2019. Retpoline Technique for Mitigating Spectre Attack. In ICEEE, 2019.Google ScholarGoogle Scholar
  14. G. Saileshwar et al. 2019. CleanupSpec: An "Undo" Approach to Safe Speculation. In MICRO, 2019.Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. M. Schwarz et al. 2019. ZombieLoad: Cross-Privilege-Boundary Data Sampling. In ACM SIGSAC, CCS, 2019.Google ScholarGoogle Scholar
  16. M. Schwarz et al. 2020. ConTExT: A Generic Approach for Mitigating Spectre. In NDSS, 2020.Google ScholarGoogle ScholarCross RefCross Ref
  17. S. van Schaik et al. 2019. RIDL: Rogue In-Flight Data Load. In IEEE Symposium on Security and Privacy, SP, 2019.Google ScholarGoogle Scholar
  18. O. Weisse et al. 2019. NDA: Preventing Speculative Execution Attacks at Their Source. In MICRO, 2019.Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. M. Yan et al. 2018. InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy. In MICRO, 2018.Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasures

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    • Published in

      cover image ACM Conferences
      DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
      July 2022
      1462 pages
      ISBN:9781450391429
      DOI:10.1145/3489517

      Copyright © 2022 ACM

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      • Published: 23 August 2022

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