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Energy-delay efficiency of VLSI computations

Published:18 April 2002Publication History

ABSTRACT

In this paper we introduce an energy-delay efficiency metric that captures any trade-off between the energy and the delay of the computation.We apply this new concept to the parallel and sequential composition of circuits in general and in particular to circuits optimized through transistor sizing. We bound the delay and energy of the optimized circuit and we give necessary and sufficient conditions under which these bounds are reached. We also give necessary and sufficient conditions under which subcomponents of a design can be optimized independently so as to yield global optimum when recomposed.We demonstrate the utility of a minimum-energy function to capture high level compositional properties of circuits. The use of this minimum-energy function yields practical insight into ways of improving the overall energy-delay efficiency of circuits.

References

  1. 1.Alain J. Martin. Towards an Energy Complexity of Computation. Information Processing Letters, 77, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2.R. Gonzalez and M. Horowitz. Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid-State Circuits, August 1997.Google ScholarGoogle Scholar
  3. 3.Paul I. Penzes and Alain Martin. Global and Local Properties of Asynchronous Circuits Optimized for Energy Efficiency. IEEE Workshop on Power Management for Real-time and Embedded Systems, Taipei, Taiwan, May 29th, 2001.Google ScholarGoogle Scholar
  4. 4.Alain Martin, Mika Nystr. om, Paul I. Penzes. ET 2: A Metric for Time and Energy Efficiency of Computation. Power-Aware Computing, Kluwer Academic/Plenum Publishers, 2002 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5.Paul I. Penzes. Energy-delay Efficiency of Asynchronous Circuits, Ph.D. Thesis (in preparation), California Institute of Technology, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6.Jose A. Tierno. An Energy-Complexity Model for VLSI Computations, Ph.D. Thesis, California Institute of Technology, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7.Anantha P. Chandrakasan, Robert W. Brodersen Low Power Digital CMOS Design Kluwer Academic Publishers, 1995 Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Energy-delay efficiency of VLSI computations

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        cover image ACM Conferences
        GLSVLSI '02: Proceedings of the 12th ACM Great Lakes symposium on VLSI
        April 2002
        194 pages
        ISBN:1581134622
        DOI:10.1145/505306

        Copyright © 2002 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 18 April 2002

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        Overall Acceptance Rate312of1,156submissions,27%

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