Saurabh N. Adya
Igor L. Markov
ABSTRACT
While a number of recent works address large-scale standard-cell placement, they typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of placeable objects. Therefore we combine floorplanning techniques with placement techniques in a design flow that solves the more general placement problem. Our work shows how to place macros consistently with large numbers of small standard cells. Our techniques can also be used to guide circuit designers who prefer to place macros by hand.
The proposed flow relies on an arbitrary black-box standard-cell placer to obtain an initial placement and then removes possible overlaps using a fixed-outline floorplanner. This results in valid placements for macros, which are considered fixed. Remaining standard cells are then placed by another call to the standard-cell placer. Empirical evaluation on ibm benchmarks shows, in most cases, wirelength improvements of 10%-50% compared to Cadence QPlace, as well as runtime improvements.
- S. N. Adya, I. L. Markov, "Fixed-outline Floorplanning Through Better Local Search", ICCD 2001, pp. 328--334. Google Scholar
Digital Library
- C. J. Alpert, J.-H. Huang and A. B. Kahng,"Multilevel Circuit Partitioning", DAC 1997, pp. 530--533. Google ScholarDigital Library
- C. J. Alpert, ISPD-98 circuit benchmarks, "The ISPD98 Circuit Benchmark Suite", http://vlsicad.cs.ucla.edu/~cheese/ispd98.html} Google ScholarDigital Library
- Cadence Inc, "Openbook documentation for QPlace", QP version 5.1.67 10/27/2000.Google Scholar
- A. E. Caldwell, A. B. Kahng and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?", DAC 2000, pp. 477--482. Google ScholarDigital Library
- A. E. Caldwell, A. B. Kahng, I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout", IEEE Trans. on CAD, vol. 19, no. 11, 2000, pp. 1304--1314. Google ScholarDigital Library
- A. E. Caldwell, A. B. Kahng, I. L. Markov, "VLSI CAD Bookshelf" http://vlsicad.eecs.umich.edu/BKGoogle Scholar
- K. Doll, F. M. Johannes and K. J. Antreich, "Iterative Placement Improvement By Network Flow Methods". IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.13, (no.10), Oct. 1994. pp. 1189--1200.Google Scholar
- S. Dutt, "Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views", ICCAD 2000, p. 254.Google Scholar
- A. B. Kahng, "Classical Floorplanning Harmful?", ISPD 2000, pp. 207--213. Google ScholarDigital Library
- G. Karypis, R. Agarwal, V. Kumar, and S. Shekhar, "Multilevel Hypergraph Partitioning: Applications in VLSI Design", DAC '97, pp. 526--529. Google ScholarDigital Library
- J.-M. Lin and Y.-W. Chang, "TCG: A Transitive Closure Graph Based Representation for Non-slicing Floorplans," DAC 2001. Google ScholarDigital Library
- Fan Mo, Abdallah Tabbara, Robert K. Brayton, "A Force-Directed Macro-Cell Placer", ICCAD2000 Google ScholarDigital Library
- H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence pair", IEEE Trans. on CAD, vol 15(12), pp. 1518--1524, 1996. Google ScholarDigital Library
- N. Sherwani, "Algorithms for VLSI Physical Design Automation", 3rd ed. Kluwer, 1999. Google ScholarDigital Library
- X. Tang, R. Tian and and D. F. Wong, "Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation", DATE 2000, pp. 106--111. Google ScholarDigital Library
- X. Tang and D. F. Wong, "FAST-SP: A Fast Algorithm for Block Placement Based on Sequence Pair", ASPDAC 2001. Google ScholarDigital Library
- M. Wang, X. Yang and M. Sarrafzadeh, "Dragon2000: Standard-cell Placement Tool for Large Industry Circuits", ICCAD 2000. Google ScholarDigital Library
- M. C. Yildiz and P. H. Madden, "Improved Cut Sequences for Partitioning Based Placement", DAC 2001.Google ScholarCross Ref
Index Terms
- Consistent placement of macro-blocks using floorplanning and standard-cell placement
Recommendations
Routability-Driven Blockage-Aware Macro Placement
DAC '14: Proceedings of the 51st Annual Design Automation ConferenceWe present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CP-trees can flexibly pack movable macros toward corners or pre-placed macros along chip boundaries circularly to optimize macro ...
Routability driven white space allocation for fixed-die standard-cell placement
ISPD '02: Proceedings of the 2002 international symposium on Physical designThe use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the ...
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning
In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and ...
Comments