skip to main content
10.1145/513918.514037acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

DRG-cache: a data retention gated-ground cache for low power

Published:10 June 2002Publication History

ABSTRACT

In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (transistor threshold voltage) process. We utilize the concept of Gated-Ground [5] (NMOS transistor inserted between Ground line and SRAM cell) to achieve reduction in leakage energy without significantly affecting performance. Experimental results on gated-Ground caches show that data is retained (DRG-Cache) even if the memory are put in the stand-by mode of operation. Data is restored when the gated-Ground transistor is turned on. Turning off the gated-Ground transistor in turn gives large reduction in leakage power. This technique requires no extra circuitry; row decoder itself can be used to control the gated-Ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25m technology to show the data retention capability and the cell stability of DRG-cache. Our simulation results on 100nm and 70nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache with less than 5% impact on execution time and within 4% increase in area overhead.

References

  1. J. Montanaro et. al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal of Solid-State Circuits, 31(11), 1703--1714, 1996.Google ScholarGoogle ScholarCross RefCross Ref
  2. V. De. Private communication.Google ScholarGoogle Scholar
  3. S. Borkar. Design challenges of technology scaling. IEEE Micro, 19(4), 23--29, July 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. S. Manne, A. Klauser, and D. Grunwald. Pipline gating: Speculation control for energy reduction. In Proceeding of the 25th Annual Int. Symp. on Comp. Archi., 32--141, 1998 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. M. D. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated-Vdd: A circuit technique to reduce leakage in cache memories. In Proceedings of ISLPED, (July 2000), ACM Press, 90--95. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. J. M. Rabaey. Digital Integrated Circuit. Prentice Hall, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. I. Fukushi, R. Sasagawa, M. Hamaminato, T. Izawa, and S. Kawashima. A low-power SRAM using improved charge transfer sense. In Proceedings of the 1998 Int. Symp. on VLSI Circuits, pages 142--145, 1998.Google ScholarGoogle Scholar
  8. L. Wei, Z. Chen, M. Johnson, K. Roy, and V. De. Design and optimization of low voltage high performance dual threshold CMOS circuits. In Proceedings of the 35th Design Auto. Conf., pages 489--494, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De. Dual-Vt SRAM cells with full-swing single-ended bit line sensing for highperformance on-chip cache in 0.13um technology generation. In Proceedings of the 2000 Int. Symp. on Low Power Elect. and Design (ISLPED), July 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Z. Chen, L. Wei, M. Johnson, K. Roy. Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks. Int. Symp. on Low Power Electronics and Design, 1998, pp.239--244. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. http://www-device.eecs.berkeley.edu/~ptm/Google ScholarGoogle Scholar
  12. N. Shibata, M. Watanabe and Y. Sato. A 2-V 300-MHz 1-Nb Current-Sensed Double-Density SRAM for Low-Power 0.3-¿m CMOS/SIMOX ASICs. IEEE Journal of Solid State Circuits, Vol. 36, No. 10, pages 1524--1537, Oct. 2001.Google ScholarGoogle ScholarCross RefCross Ref
  13. D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin-Madison, June 1997Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. T. Wada and S. Rajan. An Analytical Access Time Model for On-Chip cache Memories. IEEE Journal of Solid State Circuits, Vol. 27, No 8, pages 1147--1156,August 1992.Google ScholarGoogle ScholarCross RefCross Ref
  15. J. L Hennessy and D. A. Patterson. Computer Architecture A Quantitative Approach. Morgan Kaufmann, 2nd edition Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Narendra S., et al. Scaling of Stack Effect and its Application for Leakage Reduction. in Proceeding of ISLPED'01 (Hiltington CA, Aug 2001), ACM Press, 194--200. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. DRG-cache: a data retention gated-ground cache for low power

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in
      • Published in

        cover image ACM Conferences
        DAC '02: Proceedings of the 39th annual Design Automation Conference
        June 2002
        956 pages
        ISBN:1581134614
        DOI:10.1145/513918

        Copyright © 2002 ACM

        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 10 June 2002

        Permissions

        Request permissions about this article.

        Request Permissions

        Check for updates

        Qualifiers

        • Article

        Acceptance Rates

        DAC '02 Paper Acceptance Rate147of491submissions,30%Overall Acceptance Rate1,770of5,499submissions,32%

        Upcoming Conference

        DAC '24
        61st ACM/IEEE Design Automation Conference
        June 23 - 27, 2024
        San Francisco , CA , USA

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader