- BRAYTON, R. K., AND MCMULLEN, C. The decomposition and factorization of Boolean expressions. In Proc. IEEE International Symposium on Circuits and Systems (May 1982), pp. 49--54.Google Scholar
- CHEN, Z., AND KOREN, I. Techniques for yield enhancement of VLSI adders. In International Conference on Application Specific Array Processors (1995), pp. 222--229. Google ScholarDigital Library
- DONATH, W., KUDVA, P., STOK, L., VILLARRUBIA, P., REDDY, L., SULLIVAN, A., AND CHAKRABORTY, K. Transformational placement and synthesis. In Design Automation and Test in Europe (DATE) (Mar. 2000). Google ScholarDigital Library
- HEINEKEN, H. T.,KHARE, J., MALY, W., NAG, P., OUYANG, C., AND W. A. PLESKACZ. Cad at the design-manufacturing interface. In Proc. ACM/IEEE Design Automation Conference (June 1997). Google ScholarDigital Library
- HEINEKEN, H. T.,AND MALY, W. Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 1996), pp. 368--373. Google ScholarDigital Library
- HUIJBREGTS, E. P., XUE, H., AND A. G. JESS. Routing for reliable manufacturing. IEEE Transactions On Semiconductor Manufacturing 8, 2 (Nov. 1995), 188--194.Google ScholarCross Ref
- KOREN, I., AND KOREN, Z. Incorporating yield enhancement into the floorplanning process. IEEE Transactions On Computers 49,6 (June 2000), 1--10. Google ScholarDigital Library
- KRAVETS, V. N., AND SAKALLAH, K. A. Resynthesis of multi-level circuits under tight timing constraints. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 2002). Google ScholarDigital Library
- KUDVA, P., SULLIVAN, A., AND DOUGHERTY, W. Metrics for structural logic synthesis. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 2002). Google ScholarDigital Library
- MALY, W., HEINEKEN, H., J. KHARE, AND P. K. NAG. Design for manufacturability in submicron domain. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 1996). Google ScholarDigital Library
- R. K. PRASAD, AND I. KOREN. The effect of placement on yield for standard cell designs. In Proceedings of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Oct. 2000), pp. 3--11. Google ScholarDigital Library
- SENTOVICH, E. M. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB/ERL M92/41, UC Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.Google Scholar
- VENKATARAMAN, A., AND KOREN, I. Determination of yield bounds prior to routing. In Proceedings of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Nov. 1999), pp. 4--13. Google ScholarDigital Library
- YANG, S. Logic synthesis and optimization benchmarks user guide-version 3.0. Microelectronics Center of North Carolina, Research Triangle Park, NC, Jan. 1991.Google Scholar
Index Terms
- Understanding metrics in logic synthesis for routability enhancement
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