ABSTRACT
This paper describes a new architecture for VLSI sequential circuits and a method to control the critical races that appears subsequently in their feedback loops. This architecture reduces the number of gates resulting in lower power consumption and smaller area of implementation without incurring significant speed penalty. The critical races are controlled by introducing a delay difference between the sections of the loop. This is implemented by scaling the transmission gates already present in the circuit. This method which sizes transistors in close proximity is insensitive to variations in internal and external operating conditions. The paper presents low-power implementation of conventional circuits and of new circuits providing a higher level of integration. When used with asynchronous circuits this architecture enables the operation of circuits that are unusable using present techniques.
- Stephen H. Unger, "The Essence of Logic Circuits", 2nd edition, 1997, IEEE Press, pp.172--177. Google Scholar
- Sun Mo Kang, "Accurate Simulation of Power Dissipation in VLSI Circuits", IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October 1986.Google Scholar
- Charles Roth, "Fundamentals of Logic Design", 4th edition, 1992, West Publishing Company, p.629. Google ScholarDigital Library
Index Terms
Low power VLSI sequential circuit architecture using critical race control
Recommendations
Circuit architecture for low-power race-free programmable logic arrays
GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSIThe design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to ...
Low Power Quaternary CMOS Circuit Design
ICETET '09: Proceedings of the 2009 Second International Conference on Emerging Trends in Engineering & TechnologyIn this paper voltage mode quaternary circuits are introduced. The quaternary circuits are encoder and decoder circuit, half and full adder circuit. Quaternary operators and elements which are used in the implementation of encoder and decoder circuits, ...
Proposed low power, high speed adder-based 65-nm Square root circuit
This paper focuses on the design of a 1-bit full adder circuit using Shannon's theorem and adder-based non-Restoring and Restoring Square Rooter circuits. The proposed adder and Square Rooter schematics were developed using DSCH2 CAD tool, and their ...
Comments