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Low power VLSI sequential circuit architecture using critical race control

Published:28 April 2003Publication History

ABSTRACT

This paper describes a new architecture for VLSI sequential circuits and a method to control the critical races that appears subsequently in their feedback loops. This architecture reduces the number of gates resulting in lower power consumption and smaller area of implementation without incurring significant speed penalty. The critical races are controlled by introducing a delay difference between the sections of the loop. This is implemented by scaling the transmission gates already present in the circuit. This method which sizes transistors in close proximity is insensitive to variations in internal and external operating conditions. The paper presents low-power implementation of conventional circuits and of new circuits providing a higher level of integration. When used with asynchronous circuits this architecture enables the operation of circuits that are unusable using present techniques.

References

  1. Stephen H. Unger, "The Essence of Logic Circuits", 2nd edition, 1997, IEEE Press, pp.172--177. Google ScholarGoogle Scholar
  2. Sun Mo Kang, "Accurate Simulation of Power Dissipation in VLSI Circuits", IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October 1986.Google ScholarGoogle Scholar
  3. Charles Roth, "Fundamentals of Logic Design", 4th edition, 1992, West Publishing Company, p.629. Google ScholarGoogle ScholarDigital LibraryDigital Library

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  1. Low power VLSI sequential circuit architecture using critical race control

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    • Published in

      cover image ACM Conferences
      GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI
      April 2003
      320 pages
      ISBN:1581136773
      DOI:10.1145/764808

      Copyright © 2003 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 28 April 2003

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