Abstract
New techniques are presented for routing straight channels, L-channels, switchboxes, and staircase channels in a two-layer Manhattan-diagonal (MD) model with tracks in horizontal, vertical, and ± 45° directions. First, an O(l.d) time algorithm is presented for routing a straight channel of length l and density d with no cyclic vertical constraints. It is shown that the number of tracks h used by the algorithm for routing multiterminal nets satisfies d ≤ h ≤ (d + 1). Second, an output-sensitive algorithm is reported that can route a channel with cyclic vertical constraints in O(l.h) time using h tracks, allowing overlapping of wire segments in two layers. Next, the routing problem for a multiterminal L-channel of length l and height h is solved by an O(l.h) time algorithm. If no cyclic vertical constraints exist, its time complexity reduces to O(l.d) where d is the density of the L-channel. Finally, the switchbox routing problem in the MD model is solved elegantly. These techniques, easily extendible to the routing of staircase channels, yield efficient solutions to detailed routing in general floorplans. Experimental results on benchmarks show significantly low via count and reduced wire length, thus establishing the superiority of MD routing to classical strategies. The proposed algorithms are also potentially useful for general non-Manhattan area routing and multichip modules (MCMs).
- Berger, B., Brady, M., Brown, D., and Leighton, T. 1995. Nearly optimal algorithms and bounds for multilayer channel routing. J. ACM 42, 500--542. Google Scholar
- Burstein, M. and Pelavin, R. 1983. Hierarchical channel router. In Proceedings of the 20th Design Automation Conference. 591--597. Google Scholar
- Cataldo, A. and Fuller, B. 2001. Simplex, Toshiba prep diagonal interconnect scheme. In EE Times, June 4.Google Scholar
- Chaudhary, K. and Robinson, P. 1991. Channel routing by sorting. IEEE Trans. Comput.-Aided Des. 10, 754--760.Google Scholar
- Chen, H. H. 1987. Routing L-shaped channels in nonslicing-structure placement. In Proceedings of the 24th Design Automation Conference. 152--158. Google Scholar
- Dai, W. M., Asano, T., and Kuh, E. S. 1985. Routing region definition and ordering scheme for building-block layout. IEEE Trans. Comput.-Aided Des. 4, 189--197.Google Scholar
- Deutsch, D. N. 1985. Compacted channel routing. In Proceedings of the ICCAD. 223--225.Google Scholar
- Garey, M. R. and Johnson, D. S. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman & Co., New York, NY. Google Scholar
- Guruswamy, M. and Wong, D. F. 1988. Channel routing order for building-block layout with rectilinear modules. In Proceedings of the ICCAD. 184--187.Google Scholar
- Haruyama, S., Wong, D. F., and Fussell, D. S. 1992. Topological channel routing. IEEE Trans. Comput.-Aided Des. 11, 1177--1197.Google Scholar
- Ho, T. T. 1989. Density based general greedy channel routing. Ph.D. dissertation. Louisiana State University, Baton Rouge, LA. Google Scholar
- Ho, T. T., Iyengar, S. S., and Zheng, S. Q. 1991. A greedy channel routing algorithm. IEEE Trans. Comput.-Aided Des. 10, 204--211.Google Scholar
- Joobani, R. 1986. An Artificial Intelligence Approach to VLSI Routing. Kluwer Academic Publishers, Boston, MA. Google Scholar
- Lodi, E., Luccio, F., and Pagli, L. 1990. Routing in time square mode. Inform. Process. Lett. 35, 41--48. Google Scholar
- Lodi, E., Luccio, F., and Song, X. 1991. A 2D channel router for the diagonal model. Integration, the VLSI J. 1, 2, 111--125. Google Scholar
- Maddila, S. Rao and Zhou, D. 1989. Routing in general junctions. IEEE Trans. Comput.-Aided Des. 8, 1174--1184.Google Scholar
- Majumder, S., Nandy, S. C., and Bhattacharya, B. B. 1998. Partitioning VLSI floorplans by staircase channels for global routing. In Proceedings of the International Conference on VLSI Design. 59--64. Google Scholar
- Ohtsuki, T. 1986. Ed. Advances in CAD for VLSI, Volume 4: Layout Design and Verification. North Holland, Amsterdam, The Netherlands. Google Scholar
- Pal, R. K., Pal, S. P., Das, M. M., and Pal, A. 1995. Computing area and wire length efficient routes for channels. In Proceedings of the 8th International Conference on VLSI Design. 196--201. Google Scholar
- Pal, R. K. 2000. Multi-Layer Channel Routing: Complexity and Algorithms. Narosa, New Delhi, India.Google Scholar
- Pucknell, D. A. and Eshraghian, K. 1996. Basic VLSI Design. Prentice Hall, Engelwood Cliffs, NJ.Google Scholar
- Reed, J., Sangiovanni-Vincentelli, A., and Santomauro, M. 1985. A new symbolic channel router: YACR2. IEEE Trans. Comput.-Aided Des. 4, 208--219.Google Scholar
- Rivest, R. L. and Fiduccia, C. M. 1982. A greedy channel router. In Proceedings of the 19th Design Automation Conference (June 1982). 418--424. Google Scholar
- Sarrafzadeh, M. 1987. Channel routing problem in the knock-knee mode is NP-complete. IEEE Trans. Comput.-Aided Des. 6, 503--506.Google Scholar
- Sherwani, N. A. 1999. Algorithms for VLSI Physical Design Automation, 3rd ed., Kluwer Academic Publishers, Boston, MA. Google Scholar
- Sherwani, N. A., Bhingarde, S., and Panyam, A. 1995. Routing in the Third Dimension: From VLSI Chips to MCMs. IEEE Press, Piscataway, NJ.Google Scholar
- Shin, H. and Sangiovanni-Vincentelli, A. 1986. Mighty: A 'rip-up and reroute' detailed router. In Proceedings of the ICCAD, 2--5.Google Scholar
- Song, X. 1992. An algorithm for L-shaped channel routing in a diagonal model. IEEE Trans. Comput.-Aided Des. 11, 267--270.Google Scholar
- Sur-Kolay, S. and Bhattacharya, B. B. 1991. The cycle structure of channel graphs in nonslicible floorplans and a unified algorithm for feasible routing order. In Proceedings of the ICCD. 524--527. Google Scholar
- The, K.-S., Wong, D. F., and Cong, J. 1991. A layout modification approach to via minimization. IEEE Trans. Comput.-Aided Des. 10, 536--541.Google Scholar
- Tsai, C., Chen, S., Chen, Y., and Hu, Y. 1992. Planning strategies for area routing. In Proceedings of the European Design Automation Conference. 338--342.Google Scholar
- Tzeng, P.-S. and Sequin, C. H. 1988. Codar: A congestion-directed general area router. In Proceedings of the ICCAD. 30--33.Google Scholar
- Wang, D. 1991. Novel routing schemes for IC layout, part I: Two-layer channel routing. In Proceedings of the 28th Design Automation Conference. 49--53. Google Scholar
- Yan, J. T. and Hsiao, P.-Y. 1996. Minimizing the number of switchboxes for region definition and ordering assignment. IEEE Trans. Comput.-Aided Des. 15, 336--347. Google Scholar
- Yan, J. T. 1999. An improved optimal algorithm for bubble-sorting-based non-Manhattan channel routing. IEEE Trans. Comput.-Aided Des. 18, 2, 163--171. Google Scholar
- Yan, J. T. 2000. Three-layer bubble-sorting-based non-Manhattan channel routing. ACM Trans. Des. Automat. Electron. Syst. 5, 726--734. Google Scholar
- Yoshimura, T. and Kuh, E. S. 1982. Efficient algorithms for channel routing. IEEE Trans. Comput.-Aided Des. 1, 25--35.Google Scholar
Index Terms
- Manhattan-diagonal routing in channels and switchboxes
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