Sungju Park
ABSTRACT
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in power dissipation and testabilities for benchmark circuits.
- P. Kalla and M. J. Ciesielski., "A Comprehensive Approach to the Partial Scan Problem using Implicit State Enumera-tion", Proc. Int'l. Test Conf., pp.651--657, Nov. 1998. Google Scholar
Digital Library
- K. T. Cheng, and V. D. Agrawal, "Design of Sequential Machines for Efficient Test Generation", in Proc. of ICCAD, pp. 358--361, 1989.Google ScholarCross Ref
- Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 1978. Google ScholarDigital Library
- E. Olson, S.M. Kang, "Low-Power State Assignment for Finite State Machines", proc. IEEE Intl. Workshop on Low Power Design, pp. 63--68, April 1995.Google Scholar
- Chiusano S, Corno F, Prinetto P, Rebaudengo M, Sonza Reorda M, "Guaranteeing testability in re-encoding for low power," Test Symposium (ATS '97) Proceedings, Sixth Asian, pp. 30--35, 1997. Google ScholarDigital Library
- L.Benini and G. De. Micheli, "State assignment for low power dissipation", IEEE Journal of Solid-State Circuits, vol. 30. March 1995.Google ScholarCross Ref
Index Terms
- A new state assignment technique for testing and low power
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