Abhijit Davare
ABSTRACT
The desynchronization approach combines a traditional synchronous specification style with a robust asynchronous implementation model. The main contribution of this paper is the description of two optimizations that decrease the overhead of desynchronization. First, we investigate the use of clustering to vary the granularity of desynchronization. Second, by applying temporal analysis on a formal execution model of the desynchronized design, we uncover significant amounts of timing slack. These methods are successfully applied to industrial RTL designs.
- J. Cortadella, A. Kondratyev, L. Lavagno, C. Sotiriou, "A Concurrent Model for Desynchronization," IWLS 2003.Google Scholar
- J. P. Uyemura, "VLSI clocking and System Design" in Introduction to VLSI Circuits and Systems John Wiley & Sons, 2002.Google Scholar
- J. Rabaey, A. Chandrakasan, B. Nikolic, "Digital Integrated Circuits - Second Edition," Prentice Hall, 2003. Google ScholarDigital Library
- A. Benveniste, L. Carloni, P. Caspi, A. Sangiovanni-Vincentelli. "Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment." Proceedings of EmSoft 2003. Google ScholarDigital Library
- D. Chinnery and K. Keutzer, "Reducing the Timing Overhead," in Closing the Gap between ASIC and Custom: Tools and techniques for High-Performance ASIC design Kluwer Academic Publishers, 2002.Google Scholar
- Chu, Tam-Anh, "On the Models for Designing VLSI Asynchronous Digital Circuits," Integration, 4(2):99--113", June 1986. Google ScholarDigital Library
- T. Murata, "Petri Nets: Properties, analysis and applications," Proceedings of the IEEE, pp. 541--580, Apr. 1989.Google ScholarCross Ref
- I. E. Sutherland. Micropipelines. Communications of the IEEE, Volume 32, Number 6, 1989. Google ScholarDigital Library
- H. Hulgaard, S. M. Burns, T. Amon, and G. Borriello, "An algorithm for exact bounds on the time separation of events in concurrent systems," IEEE Transactions on Computers, 44(11):1306--1317, November 1995. Google ScholarDigital Library
- R.M. Cormack, A review of classification (with Discussion). J. Roy. Stat. Soc. A 134:321--367, 1971.Google ScholarCross Ref
Index Terms
- The best of both worlds: the efficient asynchronous implementation of synchronous specifications
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