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3D chip stacking with C4 technology | IBM Journals & Magazine | IEEE Xplore

3D chip stacking with C4 technology


Abstract:

Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a smal...Show More

Abstract:

Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.
Published in: IBM Journal of Research and Development ( Volume: 52, Issue: 6, November 2008)
Page(s): 599 - 609
Date of Publication: 30 November 2008

ISSN Information: