The IBM POWER9 processor chipset provides a variety of system memory architecture interfaces to enable highly differentiated system offerings: a high bandwidth, high capacity, highly reliable, buffered architecture; a compute-density-optimized direct DDR attach architecture; heterogeneous integration of graphics processing unit memory into the host system memory; and an agnostic, flexibly attached SCM architecture. In this paper, we explore these architectures and the targeted optimizations they provide for various classes of workloads. We also explore the development synergies and semiconductor physical design tradeoffs associated with the varying implementations, and finally, we describe several hypothetical systems that could be constructed by utilizing these memory architectures.