Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications

In this paper we present the implementation strategy and results of an energy-aware system-on-chip (SoC) that covers the baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. It is compliant with the HIPERLAN/2 standard, but it also implements critical functionality of the IEEE 802.11a standard. Two embedded processor cores, dedicated hardware, on-chip memory elements, as well as advanced bus architectures and peripheral interfaces were carefully combined and optimized for the targeted application, resulting in a proper trade-off of silicon area, flexibility and power consumption. A system-level low-power design methodology has been used, due to the fact that power consumption is the most critical parameter in electronic portable system design. The 17.5 million-transistor solution was implemented in a 0.18 micron CMOS process and performs baseband processing at data rates up to 54 Mbit/s, with average power consumption of about 550 mW.