A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture

Hardware acceleration using Field Programmable Gate Arrays (FPGAs) has become increasingly popular for computationally intensive Digital Signal Processing (DSP) applications. Unfortunately, while FPGAs have a reasonably tractable Computer Aided Design (CAD) flow and performance, they have poor power characteristics when compared to direct Application Specific Integrated Circuit (ASIC) fabrication. ASICs exhibit better performance and power than FPGAs, but require complex CAD and large Non-Recurring Engineering (NRE) costs. This paper presents a parameterizable, coarse-grained, reconfigurable fabric model that attempts to maintain FPGA-like programmability and CAD, with ASIC-like power characteristics for DSP style applications. Using this model, the architectural design space is explored by varying different parameters such as datawidth and interconnection flexibility to define an energy-efficient fabric. Additionally, the fabric is studied as a target within an automated C to hardware flow and tested on a set of select signal and image processing applications from the MediaBench benchmark suite. The fabric has been synthesized on a 160 nm cell-based ASIC fabrication process from OKI. The fabric with 4:1 multiplexers exhibits an average power improvement of approximately 130X over a Virtex-2P FPGA and 19X over Intel's XScale processor and is within 3X of an ASIC. It exhibits an average performance improvement of 17X over Intel's XScale processor and is within 2X of the Virtex-2P FPGA and 3X of an ASIC. It also shows an average energy improvement of approximately 66X over Xilinx Virtex-2P FPGA and 317X over Intel's XScale processor and is within 9X of an ASIC implementation.