Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers

Low and medium bit-rate receivers are met in a wide range of applications including the popular GSM and DECT telecommunication terminals. In principle, receivers falling in this class employ oversampling for synchronization purposes. This paper introduces a novel power-aware architecture for low and medium bit-rate digital receivers that implements power management by dynamically scaling the operation frequency. A real-life DECT receiver is used to compare the conventional and the proposed architecture. Experimental results indicate that the proposed architecture presents significantly reduced power consumption for a negligible increase in area and performance decrease. Specifically, depending on the selected oversampling ratio and the receiver structure, a 40% up to 70% power reduction has been obtained with a 2% and 1.2% increase in area and delay, respectively.