Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process

The reduction of active and passive power dissipation is one of the most important challenges in modern chip design. High-performance microprocessors are reaching the technical packaging and cooling limits, whereas power of mobile applications is limited by marginal increase in battery capacity. Numerous low-power circuit techniques have been proposed in the past. An appropriate selection remains difficult as long as comparisons are based on varying technologies and different design effort spent for their implementations. This paper closes this gap by reviewing circuit techniques for low-power high-performance design. A new quantitative comparison in a 65 nm SOI-technology of selected techniques is presented, that reveals their individual effectiveness in reducing power, as well as the design effort required for a reasonable implementation. Finally, the (dis)advantages of the various techniques are summarized.