Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating

The use of sleep transistors as power-gating devices to cut-off sub-threshold leakage stand-by currents has become a very popular solution to tackle the rise of leakage consumption in nanometer CMOS circuits. Clustered power-gating is now the de-fact standard for application of this leakage saving technique in industry. Cell clustering, sleep transistor sizing and peak current estimation are among the key steps of state-of-the-art clustered power-gating methodologies. In this work, we propose to exploit the information on the temporal variations of the discharge currents of the gates in a circuit to improve the quality of the solutions generated by an existing cell clustering algorithm. This translates to power-gated circuits with lower leakage consumption compared to implementations based clusters formed assuming a time-invariant, worst-case behavior of the currents drawn by the cells. The achieved leakage savings can be as high as 17%.