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A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures

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This work presents a novel approach for improving the energy consumption for instruction scheduling of clustered VLIW architectures. The proposed scheme is based on a preliminary cluster assignment phase implemented through partitioning and analyzing of Data Dependence Graph (DDG) and a scheduling phase using different heuristics to find an optimized schedule. The preliminary cluster assign scheme is shown to be very effective due to its global view of the whole DDG. We have implemented and evaluated the proposed scheme with UTDSP benchmarks. Results show a significant reduction in energy consumption when compared with previously proposed techniques, while also maintaining a high performance level. Energy consumption reductions are up to 41%, with average energy consumption improving ranging from 26% (2-Cluster) to 30% (4-Cluster). While performance speedup can up to 33% compared with result of list scheduling, with average speedup ranging from 25% (2-Cluster) to 30% (4-Cluster).

Keywords: CLUSTER ASSIGN; CLUSTERED VLIW ARCHITECTURE; INSTRUCTION SCHEDULING; LOW ENERGY; PERFORMANCE

Document Type: Research Article

Publication date: 01 August 2009

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  • The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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