A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications

High-level Concurrent Action-Oriented Specifications (CAOS) of hardware designs based on concurrent atomic actions can be synthesized into efficient hardware implementations as exemplified by the Bluespec Compiler. However, peak-power aware synthesis has not been available for such compilers. In this paper, we propose a technique for peak-power reduction (without unduly compromising latency) during high-level synthesis from CAOS. We demonstrate the efficacy of our technique through experimental results on some benchmark designs from Bluespec Inc. The proposed technique involves rescheduling of the actions of a design, necessitating the verification of resulting hardware against the results of standard synthesis. Thus, we also formally verify various power-minimized designs to ensure that the proposed technique preserves their correctness while reducing the peak-power.