A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits

Power consumption of clock trees in modern VLSI designs is a dominant part of the total power budget. It is thus mandatory to keep it under control. This paper introduces an approach for reducing the clock power based on optimization of clock gating. In particular, in this work we focus on theory and application of the proposed methodology both on register (flip-flop) and latch based designs. Starting from a gate-level description of the design, the methodology automatically modifies the existing clock gating structure in order to generate a set of constraints for driving the construction of the clock tree by the clock synthesis tool. The methodology has been fully integrated into an industry-strength design flow. Experiments were performed on industrial designs for a real evaluation of the effectiveness of the technique and results show that a true improvement of power savings is achievable with respect to the standard clock gating.