Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits

In this paper, a new low-swing wordline is proposed in order to reduce the oxide-tunneling leakage that is important in sub-65-nm SRAMs. This new wordline driver circuit turns off the wordline by using a higher voltage than the V_SS, relaxing the oxide stress of the access transistor. By simulating a 65-nm device using the Predictive Technology Model, this scheme was verified to be helpful in reducing not only the oxide-tunneling but also the subthreshold leakage. The simulation indicates that the total leakage is reduced by 10.3%, 18.5%, and 37.9% at the temperatures of 75 °C, 25 °C, and −25 °C, respectively. The read power is reduced by 11.2%, 12.1%, and 12.4% at the temperatures of 75 °C, 25 °C, and −25 °C, respectively. The write power is reduced by as much as 31.0%, 33.4%, and 34.8% at the temperatures of 75 °C, 25 °C, and −25 °C, respectively. A new low-swing wordline driver is proposed in order to minimize the delay penalty of the low-swing wordline to less than 1% at a temperature of 25 °C. Similarly, a new low-swing write driver is also proposed with the small delay overhead of 2% at a temperature of 25 °C.