Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells
The so-called body effect as well as internal parasitic capacitances impose strong performance limitations on complementary metal-oxide-semiconductor (CMOS) static logic gates such as decreased speed, increased power consumption and high variation of the pin-to-pin delay along the inputs.
The severity of this problem increases with the number of inputs of the gate. Like silicon-on-insulator (SOI) technologies, triple-well technologies make it possible to circumvent the body effect by using independent body terminals for each transistor in a series tree, thus allowing the practical
implementation of gates with a larger number of inputs. In this paper the authors study the viability of gates with large number of inputs using both, the traditional and the proposed design styles in a regular bulk-CMOS technology. Electrical simulation results on a set of test gates show
remarkable performance improvements in delay and power consumption of independent body gates at the expense of a significant area penalty.
Keywords: BODY EFFECT; CMOS DIGITAL GATES; HIGH SPEED; LOW POWER; PARASITIC CAPACITANCE
Document Type: Research Article
Publication date: 01 August 2011
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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