An Efficient Methodology for Full Chip Signal ElectroMigration Analysis for Advanced Technology Node Designs

ElectroMigration (EM) is becoming an increasingly important challenge in advanced process technologies due to reducing interconnect widths, increasing inter-connect lengths (increasing die-size), increasing on-die temperatures, and increasing complexity of ElectroMigration rules (provided by foundry). Hence traditional approaches of attempting to create correct by construction interconnect design is becoming increasingly inadequate and found to leave numerous real EM violations on design. Further, higher performance goals and current densities at these nodes, necessitate checking ElectroMigration not just for average currents but also peak and rms (self-heat) currents. In this paper, we review some of these challenges and then describe a practical CAD methodology for Signal ElectroMigration analysis for large SOC designs at advanced technology nodes using EDA tool RedHawk-SEM. We present results and observations from application of this methodology on some high performance large SOC designs at 45 nm.