A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization

As the CMOS technology scales down to nanometer regime the process variations have profound effect on circuit attributes. Meeting timing and power constraints under such process variations in nano-CMOS circuit design is becoming increasingly difficult. A shifting from worst-case based analysis and optimization to statistical or probability based analysis and optimization at every level of circuit abstraction has happened. This paper presents a Taylor Expansion Diagram (TED) based approach for statistical optimization during high-level synthesis (HLS). A variation-aware simultaneous scheduling and resource binding algorithm is proposed which maximizes the power yield under timing yield and performance constraint. For this purpose, a multiple-oxide thickness (multi-T_ox ) library at 45 nm CMOS is characterized under process variation. The delay and power distribution of different functional units are accurately analyzed. The proposed variation-aware algorithm uses those components for generating low-power register-transfer level (RTL) descriptions under a given timing yield and performance constraint. The experimental results show significant improvement as high as 95% on leakage power yield under given constraints.