Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations

The dramatic increase in leakage current has become a major issue for future IC designs. Moreover, as process variability in nano-scaled CMOS technologies induces a large spread of leakage power, leakage variability cannot be neglected anymore. In this paper, the predominant physical process parameters for static power consumption variation are analyzed for a 32 nm technology node. The presented results are confirmed by a Principal Component Analysis (PCA). A comparative analysis with 45 nm technology results is presented. In addition, a Slice Inverse Regression (SIR) method is used to study, in 32 nm, the evolution of the impact of several parameters, like the gate-length, the oxide thickness and the doping, with the supply-voltage.