Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits

Test power during scan loading or unloading is proven to be larger than that of capture and functional modes. Scan cell gating has been demonstrated to be an effective method in reducing shift power during test application. However, the gating logic not only introduces chip area overhead, reduces timing margin, affect test coverage, but also increases power in capture mode. This paper analyzes the power behavior in scan shift mode, and proposes a partial gating flow that calculates circuit toggling probability to identify a group of power sensitive cells. The toggling rate reduction tendency is demonstrated to be useful in estimating a partial gating ratio so as to achieve a desired shift power reduction rate for a design. To ensure power safety across entire test session, the toggling reduction rate metric is enhanced to consider the effect of capture power increase. A complementary pair of weight factors can be assigned to guide the power sensitive cell selection process, thus can adjust the power behavior in both shift and capture modes, and achieve an overall balanced power safety. The impact of gating scheme on fault coverage is also analyzed using our flow. The signal probability metric along with the proposed gating flow are adopted to fulfill power requirements in different practical test environments when considering current limits of both circuit and tester.