Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns

It is a well known fact that switching activity during test mode is much higher when compared with functional mode. Excessive number of transitions in a circuit causes power supply noise, hot spots and performance degradation which reduce transition delay fault (TDF) test quality and chip reliability. This paper introduces a layout-aware TDF pattern evaluation procedure integrated into current automatic test pattern generation (ATPG) flow to exclude patterns generating transitions above a certain threshold and to replace them with new patterns meeting the threshold. In addition, a new design-for-testability (DFT) technique is developed to localize and limit transitions into specific portions of a design layout. The localization grants to control stress on power distribution network of the design. Our comprehensive simulation results over several benchmarks demonstrate that incorporating the new DFT technique and the pattern evaluation flow can effectively reduce peak switching activity in the design during test. The presented method does not incur area overhead, is independent of patterns, and can be easily integrated into today's physical design and pattern generation flows.