CMOS Phase-Locked Loop Circuits and Hot Carrier Effects

Three CMOS phase-locked loop (PLL) integrated circuits are designed in 0.5 μmn-well CMOS process using single-ended voltage-controlled oscillator, differential voltage-controlled oscillator and LC voltage-controlled oscillator circuits. Effects of hot carriers on jitter and phase noise on performance of phase-locked loops are investigated and analyzed. On-chip measured experimental results show that for the phase-locked loop with the single-ended voltage-controlled oscillator working at 500 MHz carrier frequency, phase noise is –76 dBc/Hz at 10 kHz offset frequency and –119 dBc/Hz at 1 MHz offset frequency. For the phase-locked loop with differential voltage-controlled oscillator working at 500 MHz, phase noise reaches –82 dBc/Hz at 1 kHz offset frequency and –122 dBc/Hz at 1 MHz offset frequency. Tuning frequencies of the two phase-locked loops decrease about 100–200 MHz when subjected to four hours of hot carrier stress. For the phase-locked loop with the differential voltage-controlled oscillator, a 50 ps RMS jitter increase is observed under hot carrier stress. A 3 V 1.2 GHz phase-locked loop (PLL) frequency synthesizer is implemented using LC VCO and a low power dual-modulus prescaler in 0.5 μm CMOS technology. The LC VCO working range is from 900 MHz to 1.4 GHz. Fully differential LC VCO is used to provide a high oscillation frequency. The effect of hot carriers is studied through the varactor in LC VCO. It is clearly shown that MOSFET CV curve shifts toward left by 0.4 V due to hot carrier effect. The Current Mode Logic (CML) technique is used in designing high speed D flip flop in the dual-modulus prescaler circuits for low power consumption. The power consumption of the PLL chip is under 30 mW. The phase noise of LC VCO is –60 dBc/Hz at 100 Hz offset frequency and –118 dBc/Hz at 100 kHz offset frequency. The power spectrum density of the PLL carrier frequency is decreased by about 5 dBm with the hot carrier effect.