A Bus Switch Coding System with Minimal Hardware Demand

This paper introduces the best architecture for a novel low-power encoding system suitable for high bandwidth off-chip data buses. The technique, known as Bus Switch, reorders dynamically the lines of a bus in agreement to a permutation scheme such to minimize the total bus switching activity, responsible for the consumption of dynamic energy. The idea was to reduce the area, power and latency of the permutation circuits using fixed-scheme scrambling units. Moreover, I replaced the toggle count calculation and evaluation circuits with a hierarchical arrangement of analog comparators, representing the bus toggle binary string as a voltage value. I designed the Bus Switch encoder and decoder in semiconductor technologies at 90, 65 and 45 nanometers. The results confirmed that the proposed Bus Switch minimized the required transistors number and the related area and energy consumptions, extending the Bus Switch's field of application.