Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance

Power-gating is a widely used technique for leakage power reduction in nanoscale CMOS circuits. The amount of leakage saving depends on the W/L ratio of the power-gating transistor. While power-gating transistors with low W/L ratios help save leakage, they may adversely affect the active-mode delay of the circuits in which they are employed. Very large W/L ratios, on the other hand, could themselves contribute to considerable leakage. In this paper, a probability-based approach to size the power-gating transistor has been described for full adders and applied to five different full adder circuits. Using this approach, optimal W/L ratio values have been derived for these circuits. The effectiveness of the derived optimal W/L ratio values in a large circuit has been verified by applying them to an 8-bit Ripple Carry Adder. Results indicate that using the optimal W/L ratio for the power-gating transistor could help achieve more leakage savings when compared to higher W/L ratios without causing significant delay penalties at the same time.