A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation
This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y-access MOS (column-direction access
transistor) can improve dummy-read cells' noise margin and isolate the pre-charge noise from bit-lines in synchronous or asynchronous clock operation. The paper also proposes a scheme of combining the row access transistor and sharing bit-line with an adjacent bit-cell. This scheme can reduce
the bit-line number to half and mitigate the current consumption of the write/read buffer caused by precharging the bit-line to VDD. Furthermore, Y-passgate (column direction access transistor) numbers can also be reduced to half with the proposed DP 10T SRAM architecture. The result
shows that write/read buffer current consumption was reduced by over 30%, compared to the conventional DP 8T structure from 1.4 V to 0.6 V VDD.
Keywords: 10T; DUAL-PORT; SRAM; WRITE/READ DISTURB
Document Type: Research Article
Publication date: 01 August 2012
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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