Leakage-Aware Speculative Branch Target Buffer

Modern processors are highly dependent on the speculation of the control flow of the application by means of branch prediction. To provide accurate speculation of the direction of each branch, processors need a complex branch predictor with a large Branch Target Buffer. The branch target buffer is a memory area in which the target addresses of the taken branches are stored. As the size of the buffer grows it can provide more accurate speculation but it will need more power for the branch target buffer memory area. Most of the branch target buffer, however, is not needed at any certain point of the working period of the processor. In this work, we introduce Leakage-Aware Speculative Branch Target Buffer to reduce the static power dissipation of the branch target buffer while trying to keep up with the performance of the conventional branch target buffer architecture. This can be done by introducing a predictive technique in a way that the buffer speculatively activates the next needed entry in the memory while putting the rest of the cells in the low power or “Drowsy” state. The results show that on average our method dissipates about one third of the static power compared to a conventional branch target buffer while maintaining performance.