Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors

In this work we propose using heterogeneous interconnects in power-aware chip multiprocessors (also referred to as Helia). Helia improves energy efficiency in snoop-based chip multiprocessors as it eliminates unnecessary activities in both interconnect and cache. This is achieved by using innovative snoop filtering mechanisms coupled with wire management techniques. Our optimizations rely on the observation that a high percentage of cache mismatches could be detected by utilizing a small subset but highly informative portion of the tag bits. Helia comes in two variations: source-based (S-Helia) and destination-based (D-Helia). S-Helia relies on a global snapshot of remote caches collected in the snoop controller to detect possible remote tag mismatches. D-Helia, on the other hand, reduces power by storing and monitoring a low resolution snapshot of each remote cache at destination nodes. Power is reduced as (a) our wire management techniques permit slow transmission of a subset of tag bits while tag mismatches are being detected and (b) we avoid cache access for detected mismatches. Our evaluation shows that S-Helia reduces power in interconnect (dynamic: 50%, static: 50% to 55%) and cache tag array (dynamic: 32%, static: 50%) while improving average performance up to 4.4%. D-Helia, on the other hand, reduces power in interconnect (dynamic: 23%, static: 28%) and cache tag array (dynamic: 50%, static: 30%) while improving average performance up to 3.5%.