Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability

In this paper, we investigate the effects of variation of two process parameters, Lightly Doped Drain (LDD) implantation energy and Channel Doping Dose (CDD) variations, on Flash memory performances (programming efficiency, consumption energy). The reliability aspect is taken into account with endurance experiments to evaluate the impact of these process variations on memory cell cycling induced degradation. The variation aspects are presented through process corners dedicated to LDD and CDD fabrication steps. We demonstrate that by adjusting the channel doping dose and the LDD implantation energy, Flash cells performances improvements can be achieved in order to find the best trade-off, depending of the memory application.