Power Estimation at Different Abstraction Levels for Wireless Baseband Processors

The Software-Defined Radio (SDR) solutions which are expected to be used widely in future smartphones, have tight processing time and power consumption constraints. During the SoftWare (SW) phase of the application mapping on these SDR platforms, i.e., when the application is mapped, compiled and evaluated by the Instruction Set Simulator (ISS), SW designers are worried only about the timing and not about the power consumption. Power consumption is analyzed only later during the HardWare (HW) phase, when the application is simulated at gate-level on the synthesized processor. In this paper we present a methodology which analyzes both, the timing aspects as well as the power aspects at different abstraction levels for implementation of different wireless standards using a wireless baseband processor. We use our gate-level estimation flow to obtain accurate performance and power numbers. For timing aspects we use both the ISS and gate-level simulations. For power aspects we derive a power model from gate-level simulation results and integrate it into the ISS. These obtained timing and power numbers are integrated into our high-level DART platform simulator to obtain the global view on the timing and power consumption for different wireless applications. Our proposed flow proposed can be used at an early stage of future SDR designs to obtain a profound insight on the timing and power consumption of mapped applications.