A Semi-Analytical Approach to Study the Energy Consumption of On-Chip Networks Testing
A semi-analytical approach is proposed to calculate link testing energy consumption of mesh NoC using IEEE JTAG standard. A transistor-level model is presented to calculate dynamic energy and HSPICE simulation is used for static energy. Furthermore, the switching activities and test
time are calculated using a special purpose cycle-accurate NoC simulator. The results are integrated into the proposed model to obtain total energy consumption and verified with HSPICE simulation. Using the model, the most energy-consuming parts, power peaks, area overhead, and test time are
calculated and identified. As a result the model is useful to study the trade-offs in JTAG test architecture implemented on NoC and optimise it in terms of power, test time and area.
Keywords: ANALYTICAL MODEL; AREA; ENERGY; JTAG; ON-CHIP NETWORKS; POWER; TEST; TEST TIME
Document Type: Research Article
Publication date: 01 August 2013
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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