Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits

In this paper, we propose a transistor level approach for leakage as well as variability issues reduction. Modern battery operated portable systems require long life battery with large functionality on single substrate buffer. Leakage current and variability issues are increasing rapidly while moving towards the ultra deep submicron regime; and hence affect the performance characteristics of the implemented circuits. Leakage power dissipation as well as process, voltage and temperature variations are the crucial concern in nanoscale CMOS circuits since increasing importance of battery operated portable systems. In this article; we have presented a novel transistor level technique to mitigate leakage as well as process, voltage and temperature variations for designing the energy efficient reliable CMOS circuits in nanoscale regime. The simulated results are obtained using HSPICE tool with predictive technology process model file at 32 nm technology node. The process, voltage and temperature variations are evaluated through Monte-Carlo simulations performed on 1000 samples. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique. The power delay product and energy uncertainties of the approach are 3X less as compared to conventional design and hence more suitable for future energy efficient nanoscale CMOS circuits.