Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop

This paper presents process variation compensations applied to Ultra Low Power PLL (Phase Locked Loop), in order to decrease spurious level created by FPD (Fractional Phase Divider) architecture. It uses internal phases propagation delays (TPD) of VCRO (Voltage Controlled Ring Oscillator) to achieve fractional comparison to F _REF (Reference Frequency). The VCRO is designed in 28 nm FDSOI technology and optimized for Bluetooth application. In fact, it is demonstrated, that due to the process variation, the use of bulk CMOS for sub-28 nm becomes very challenging and severely limits area and supply scaling. Thin-film technology such as Ultra-Thin Body and Box (UTBB) FDSOI however, should be a good candidate to overcome this problem. The possibility of the back gate biasing, offered by this technology, is used to calibrate the PLL. Three loops have been investigated to ensure PLL operation over all Process Voltage and Temperature (PVT) cor- ners: a Frequency Locked Loop (FLL) corrects nominal frequency deviation, a Duty Cycle Correction (DCC) balances PMOS/NMOS conductivity and a multiplexed PLL loop unifies RO TPD's to reach a ± 1% maximum deviation, corresponding to spurious level attenuation from –60 dBc@1 MHz to –90 dBc@1 MHz.