Power Aware Architecture Exploration for Field Programmable Gate Arrays

Reducing power has become a top priority when designing new FPGA architectures. A key tool in this endeavour is a power model that predicts the impact of architectural enhancements. We present a new power model, which unlike past models, supports modern FPGA features such as fracturable look-up tables (LUTs), hard blocks, and user-designed logic blocks. We show that for a common architecture, 40% of power is from routing, 28% from logic blocks, 6% from the clock, with the remaining from memories and multipliers. Fracturable LUT architectures raise power by 5–11%; however, by replacing a fully populated crossbar with a one-third populated crossbar, power is reduced by 8%.