Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture

Fast Fourier Transform is an integral part of OFDM systems. FFT is the most compute intensive operation that critically affects the OFDM system performance. In order to support the various OFDM standards, a scalable and reconfigurable FFT architecture is necessary. This paper presents an energy efficient and scalable FFT architecture, which can be dynamically reconfigured to adapt to specifications of different standards. The proposed architecture is based on Radix-4 ⁿ algorithm and uses a parallel-pipelined unrolled architecture. The proposed architecture can be scaled to support FFTs of sizes upto 64 K points. As a proof of concept, FFT architecture for computation of FFTs of sizes 64 to 4096 point has been implemented in UMC 65 nm 1P10M CMOS process with a maximum clock frequency of 125 MHz and area of 1.05 mm². The power consumption at 40 MHz is 33.5 mW for the computation of 4096 point FFT. Energy efficiency (FFTs per unit of energy) of the proposed architecture is 1176 for 1 K point, 584 for 2 K point and 291 for 4 K point FFTs at 40 MHz. The proposed architecture shows better performance in terms of scalability and energy efficiency when compared to existing implementations.